VFB

Compensation

Ramp

PWM

t

ON

t

OFF

VREF

UDG-10209

VFB

VREF

PWM

t

ON

t

OFF

UDG-10208

TPS53353

www.ti.com

SLUSAK2B – AUGUST 2011 – REVISED FEBRUARY 2015

Table 1. Resistor and Switching Frequency (continued)

SWITCHING

CONNECTIONS

FREQUENCY

VALUE (k

Ω)

CONNECT TO

(kHz)

619

GND

400

OPEN

n/a

500

866

VREG

650

309

VREG

750

124

VREG

850

0

VREG

970

The off-time is modulated by a PWM comparator. The VFB node voltage (the mid-point of resistor divider) is

compared to the internal 0.6-V reference voltage added with a ramp signal. When both signals match, the PWM

comparator asserts a set signal to terminate the off time (turn off the low-side MOSFET and turn on high-side

MOSFET). The set signal is valid if the inductor current level is below the OCP threshold, otherwise the off time

is extended until the current level falls below the threshold.

Figure 35 and Figure 36 show two on-time control schemes.

Figure 35. On-Time Control Without Ramp

Figure 36. On-Time Control With Ramp

Compensation

Compensation

7.3.3 Ramp Signal

The TPS53353 adds a ramp signal to the 0.6-V reference in order to improve jitter performance. As described in

the previous section, the feedback voltage is compared with the reference information to keep the output voltage

in regulation. By adding a small ramp signal to the reference, the signal-to-noise ratio at the onset of a new

switching cycle is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is

controlled to start with –7 mV at the beginning of an on-cycle and becomes 0 mV at the end of an off-cycle in

steady state.

During skip mode operation, under discontinuous conduction mode (DCM), the switching frequency is lower than

the nominal frequency and the off-time is longer than the off-time in CCM. Because of the longer off-time, the

ramp signal extends after crossing 0 mV. However, it is clamped at 3 mV to minimize the DC offset.

7.3.4 Adaptive Zero Crossing

The TPS53353 has an adaptive zero crossing circuit which performs optimization of the zero inductor current

detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and

compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. It

prevents SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too

early detection. As a result, better light load efficiency is delivered.

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