TPS53353

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SLUSAK2B – AUGUST 2011 – REVISED FEBRUARY 2015

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 1.5 V to 22 V (4.5 V to 25 V biased).

This input supply must be well regulated. Proper bypassing of input supplies and internal regulators is also

critical for noise performance, as is PCB layout and grounding scheme. See the recommendations in the Layout

section.

10 Layout

10.1 Layout Guidelines

Certain points must be considered before starting a layout work using the TPS53353.

•

The power components (including input/output capacitors, inductor and TPS53353) should be placed on one

side of the PCB (solder side). At least one inner plane should be inserted, connected to ground, in order to

shield and isolate the small signal traces from noisy power lines.

•

All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed

away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer(s) as ground

plane(s) and shield feedback trace from power traces and components.

•

Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC

current loop.

•

Because the TPS53353 controls output voltage referring to voltage across VOUT capacitor, the top-side

resistor of the voltage divider should be connected to the positive node of the VOUT capacitor. The GND of

the bottom side resistor should be connected to the GND pad of the device. The trace from these resistors to

the VFB pin should be short and thin.

•

close to the device as possible. Use the common GND via to connect them to GND plane if applicable.

•

Place the VDD and VREG decoupling capacitors as close to the device as possible. Ensure to provide GND

vias for each decoupling capacitor and make the loop as small as possible.

•

The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor,

should be as short and wide as possible.

•

ceramic output capacitor. The AC coupling capacitor (C2 in Figure 41) should be placed near the device, and

R7 and C1 can be placed near the power stage.

•

Use separated vias or trace to connect LL node to snubber, boot strap capacitor and ripple injection resistor.

Do not combine these connections.

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