ML4819CS datasheet(7/15 Pages) MICRO-LINEAR

7 / 15 page

ML4819

SLOPE COMPENSATION

Slope compensation is accomplished by adding 1/2 of the

current flowing out of pin 12 to pin 1 (for the PFC section

and pin 9 (for the PWM section). The amount of slope

compensation is equal to (IRAMP COMP/2) ¥ RL where RL is

the impedance to GND on pin 1 or pin 9. Since most of

the PWM applications will be limited to 50% duty cycle,

slope compensation should not be needed for the PWM

section. This can be defeated by using a low impedance

load to the current sense on pin 9.

500

400

300

200

100

200

300

400

500

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

1. 5V

SINE INPUT CURRENT (µA)

Figure 8. Gain Modulator Linearity

ENABLE

VREF

GEN.

INTERNAL

BIAS

5V VREF

VCC

–

Figure 9. Under-Voltage Lockout Block Diagram

TA = 25 C

102030

VCC, SUPPLY VOLTAGE (V)

Figure 10a. Total Supply Current vs. Supply Voltage

START-UP

1020

30405060

TEMPERATURE ( C)

OPERATING

CURRENT

Figure 10b. Supply Current (ICC) vs. Temperature

OSC

RSC

VREF

IR(SC)

TO PIN 9

TO PIN 1

IR(SC) " 2

RAMP COMP

SLOPE

COMPENSATION

Figure 7. Slope Compensation Circuit

UNDER VOLTAGE LOCKOUT

On power-up the ML4819 remains in the UVLO condition;

output low and quiescent current low. The IC becomes

operational when VCC reaches 16V. When VCC drops

below 10V, the UVLO condition is imposed. During the

UVLO condition, the 5V VREF pin is “off”, making it

usable as a status flag.

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