ML4819CS datasheet(12/15 Pages) MICRO-LINEAR

12 / 15 page

ML4819

OVERVOLTAGE PROTECTION (OVP) COMPONENTS

The OVP loop should be set so that there is no interaction

with the voltage control loop. Typically it should be set to

a level where the power components are safe to operate.

Ten to fifteen volts above VOUT seems to be adequate.

This sets the maximum transient output voltage to about

395V.

By choosing the high voltage side resistor of the OVP

circuit the same way as above i.e. R7 = 356K then R8 can

be calculated as:

REF

OVP

REF

356

395

4 564

−

Ω

(20)

Choose 4.53k

W, 1%.

Note that R5, R6, R7 and R8 should be tight tolerance

resistors such as 1% or better.

OFF-LINE START-UP AND BIAS SUPPLY GENERATION

The Start-Up circuit in Figure 12 can be either a “bleed

resistor” (39k

W, 2W) or the circuit shown in Figure 13. The

bleed resistor method offers advantage of simplicity and

lowest cost, but may yield excessive turn-on delay at low

line.

When the voltage on pin 15 (VCC) exceeds 16V, the IC

starts up. The energy stored on the C21 supplies the IC

with running power until the supplemental winding on T3

can provide the power to sustain operation.

PWM SECTION

The PWM section in Figure 12 is a two switch forward

converter, shown in Figure 14 below for clarity. This fully

clamped circuit eliminates the need for very high

voltage MOSFETs. Flyback topology is also possible with

the ML4819.

ENHANCEMENT CIRCUIT

The power factor enhancement circuit (inside the dotted

lines) in Figure 11 is described in Application Note 11. It

improves the power factor and lowers the input current

harmonics. Note that the circuit meets IEC1000-3-2

specifications (with the enhancement circuit installed) on

the harmonics by a large margin while correcting the

input power factor to better than 0.99 under most steady

state operating conditions.

R33

Ω

R31

510k

Ω

R32

Ω

2N2222

C21

0.1

D16

22V

VREF

TO VCC

OUT

R30

4.3k

Ω

IRF821

D15

1N4001

START-UP

CIRCUIT

Figure 13. Start-Up Circuit

D12

D11

ML4819

385VDC

Figure 14. Two-Switch Forward Converter

This regulator (Figure 12) uses current mode control.

Current is sensed through R24 and filtered for high

frequency noise and leading edge transient through T23

and C14. The main regulation loop is through PWM B. The

TL431 (U3) in the secondary serves as both the voltage

reference and error amplifier. Galvanic isolation is

provided by an optocoupler (U2) which provides a current

command signal on pin 8. Loop compensation is provided

by R29 and C20. The output voltage is set by:

OUT =+









25 1

(21)

The control loop is compensated using standard

compensation techniques.

Current is limited to a threshold of 2A (1V on R24). The duty

cycle is limited in this circuit to below 50% to prevent

transformer (T3) core saturation. The maximum duty cycle

limit of 45% is set using a threshold of VREF/2 on pin 7.

the circuit in Figure 12 can be modified for voltage mode

operation by utilizing the slope current which appears on

pin 9 as show in figure 15 below.

The ramp amplitude appearing on pin 9 will be:

=×

()

(22)

where R18 is the slope compensation resistor. Since this

circuit operates with a constant input voltage (as supplied

by the PFC section) voltage feed-forward is unnecessary.

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