ADC31JB68RTA25 datasheet(4/74 Pages) TI1

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VA3.0

VA1.2

VA3.0

SYNC+

50:

SYNC-

2k:

1.8V

1.5k:

34k:

3pF

2k:

1.8V

VA3.0

SYSREF+

SYSREF-

50:

0.5V

50:

12k:

VA1.2

3k:

1k:

AGND

VA3.0

CLKIN+

CLKIN-

50:

0.5V

50:

10k:

AGND

VA1.2

VA3.0

VIN+

VIN-

100:

VCM

VA3.0

ADC31JB68

SLASE60A – SEPTEMBER 2015 – REVISED SEPTEMBER 2015

www.ti.com

Pin Functions

TYPE or DIAGRAM

DESCRIPTION

NAME

NO.

INPUT/REFERENCE

Differential analog input pins.

VIN+

The differential full-scale signal level is 1.7 Vpp. Each input pin is terminated to the

4, 5

internal 1.6V common-mode reference with a 100

Ω resistor for a 200 Ω total

VIN–

differential termination.

Input Interface Common mode voltage.

This pin must be bypassed to AGND with a low ESL (equivalent series inductance)

0.1 µF capacitor that is placed as close to the pin as possible to minimize stray

inductance. A 10 µF capacitor should also be placed in parallel. It is recommended to

VCM

use VCM to provide the common mode voltage for the differential analog inputs. The

input common-mode bias is provided internally for the ADC input, therefore external

use of VCM is recommended but not strictly required. The recommended decoupling

is always required.

CLOCK/SYNC

Differential device clock input pins.

AC coupling is recommended for coupling the clock input to these pins. DC biasing of

CLKIN+

the clock receiver is provided internally. Each pin is internally terminated to the

11, 12

500mV DC bias with 50

Ω resistor for a 100 Ω total internal differential termination

CLKIN–

resistor. Sampling occurs on the falling edge of the differential signal (CLKIN+)

−

(CLKIN-).

Differential SYSREF signal input pins.

Each pin is internally terminated to the DC bias with a large resistor. An internal 100

SYSREF+,

17, 18

Ω differential termination is provided therefore an external termination is not required.

SYSREF–

Additional resistive components in the input structure give the SYSREF input a wide

input common mode range.

Differential SYNCb signal input pins.

DC coupling is required for coupling the SYNCb signal to these pins. Each pin is

internally terminated to the DC bias with a large resistor. An internal 100

Ω differential

SYNCb+

19, 20

termination is provided therefore an external termination is not required. Additional

SYNCb–

resistive components in the input structure give the SYNCb input a wide input

common mode range. The SYNCb signal is active low and is therefore asserted when

the voltage at SYNCb+ is less than at SYNCb–.

SERIAL INTERFACE (SPI)

SPI Interface Serial Clock pin.

SCLK

Serial data is shifted into and out of the device synchronous with this clock signal.

Compatible with 1.2–3.0V CMOS logic levels.

SPI Interface Chip Select pin.

When this signal is asserted, SCLK is used to clock input serial data on the SDI pin or

output serial data on the SDO pin. When this signal is de-asserted, the SDO pin is

CSB

high impedance and the input data is ignored. Active low. A 1k

Ω pull-up resistor to the

VA1.8 supply is recommended to prevent undesired activation of the SPI bus.

Compatible with 1.2–3.0V CMOS logic levels.

SPI Interface Data Input pin.

SDI

Serial data is shifted into the device on this pin while the CSB signal is asserted.

Compatible with 1.2-3.0V CMOS logic levels.

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