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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADC31JB68RTA25 Datenblatt(PDF) 1 Page - Texas Instruments |
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ADC31JB68RTA25 Datenblatt(HTML) 1 Page - Texas Instruments |
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1 / 74 page  Frequency [MHz] 0 25 50 75 100 125 150 175 200 225 250 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Product Folder Sample & Buy Technical Documents Tools & Software Support & Community ADC31JB68 SLASE60A – SEPTEMBER 2015 – REVISED SEPTEMBER 2015 ADC31JB68 Single Channel 16-bit 500 Msps Analog to Digital Converter 1 Features 2 Applications 1 • Single Channel • High IF Sampling Receivers • 16-Bit Resolution • Broadband Wireless • Maximum Clock Rate: 500 Msps • Microwave Receivers • Small 40-Pin QFN Package (6 x 6 mm) • Cable CMTS, DOCSIS 3.1 Receivers • Input Buffer Input Bandwidth (3 dB): 1300 MHz • Communications Test Equipment • Aperture Jitter: 80 fs • Digitizers • On Chip Clock Divider: /1, /2, /4 • Software Defined Radio (SDR) • On Chip Dither • Radar and Antenna Arrays • Consistent Dynamic Performance Using 3 Description Foreground and Background Calibration The ADC31JB68 is a low power, wide bandwidth 16- • Input Amplitude and Phase Adjustment bit 500 MSPS analog-to-digital converter (ADC). The • Input Full Scale: 1.7 Vpp buffered analog input provides uniform input • Power Supplies: 1.2/1.8/3 V impedance across a wide frequency range while minimizing sample-and-hold glitch energy. It is • JESD204B Interface designed to sample input signals of up to 1.3 GHz. – Subclass 1 Compliant The ADC31JB68 provides excellent spurious-free – 2 Lanes at 5 Gbps dynamic range (SFDR) over a large input frequency • Support for Multi-chip Synchronization range with very low power consumption. On-chip • Key Specifications dither provides an very clean noise floor. Embedded foreground and background calibration ensures – Power Dissipation: 915 mW at 500 Msps consistent performance over the temperature range – Performance at fin = 210 MHz at –1 dBFS and minimizes part to part variation. – SNR: 69.3 dBFS It supports the JESD204B serial interface with data – NSD: –153.3 dBFS/Hz rates up to 5 Gbps on each of 2 lanes, enabling high – SFDR: 80 dBc system integration density. – Non-HD2,HD3: –91 dBFS The device comes in a 40-pin QFN (6 x 6 mm) – Performance at fin = 450 MHz at –1 dBFS package. – SNR: 67 dBFS Device Information(1) – NSD: –151 dBFS/Hz PART NUMBER PACKAGE BODY SIZE (NOM) – SFDR: 77 dBc HD2,3 ADC31JB68 WQFN (40) 6.00 mm × 6.00 mm – Non-HD2,HD3: –89 dBFS (1) For all available packages, see the orderable addendum at the end of the datasheet. SPACE Transmitted Eye at Output of 18-inch, 5-mil. FR4 Spectrum with -1 dBFS 450 MHz Input Microstrip Trace at 5 Gb/s with Optimized De-Emphasis 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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