LXT351 datasheet(14/46 Pages) INTEL

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LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation

Datasheet

2.2.2

Transmit Monitoring

The transmitter includes a short circuit limiter that limits the current sourced into a low impedance

load. The limiter automatically resets when the load current drops below the limit. The current is

determined by the interface circuitry (total resistance on transmit side).

The Performance Status Register (PSR) flags open circuits in bit PSR.DFMO. A transition of

DFMO can provide an interrupt, and its transition sets bit TSR.DFMO = 1. Writing a 1 in bit

ICR.CDFMO clears the interrupt; leaving a 1 in the bit masks that interrupt.

2.2.3

Transmit Drivers

The transceiver transmits data as a 50% line code as shown in Figure 3. To reduce power

consumption, the line driver is active only during transmission of marks, and is disabled during

transmission of spaces. Biasing of the transmit DC level is on-chip.

2.2.4

Transmit Idle Mode

Transmit Idle mode allows multiple transceivers to be connected to a single line for redundant

applications. When TCLK is not present, Transmit Idle mode becomes active, and TTIP and

TRING change to the high impedance state. Remote or Dual Loopback, TAOS or any internal

transmit patterns temporarily disable the high impedance state.

2.2.5

Transmit Pulse Shape

As shown in Table 8 on page 25, the transmitted pulse shape is established by bits EC1 through

EC3 of Control Register #1 (CR1).

The transceiver produces DSX-1 pulses for short-haul T1 applications (settings from 0 dB to +6.0

dB of cable) or G.703 pulses for E1 applications. Shaped pulses are applied to the AMI line driver

for transmission onto the line at TTIP and TRING. Refer to the Test Specifications section for

pulse mask specifications.

Figure 3. 50% Duty Cycle Coding

Bit Cell

LXT351 Datenblatt(PDF) 14 Page - Intel Corporation