CLC446AMC datasheet(5/12 Pages) NSC

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DC Gain (unity gain buffer)

The recommended Rf for unity gain buffers is 453Ω. Rg

is left open. Parasitic capacitance at the inverting node

may require a slight increase of Rf to maintain a flat

frequency response.

DC Gain (inverting)

The inverting DC voltage gain for the configuration

shown in Figure 2 is

Figure 2: Inverting Gain

The normalized gain plots in the

Typical Performance

Characteristics

section

show

different

feedback

resistors (Rf) for different gains. These values of Rf are

recommended for obtaining the highest bandwidth with

minimal peaking. The resistor Rt provides DC bias for the

non-inverting input.

For |Av| < 5, use linear interpolation on the nearest Av val-

ues to calculate the recommended value of Rf. For |Av|

≥ 5, the minimum recommended R

f is 200Ω.

Select Rg to set the DC gain:

At large

gains, Rg becomes small and will load the previous stage.

This can be solved by driving Rg with a low impedance

buffer like the CLC111, or increasing Rf and Rg.

See the

AC Design (small signal bandwidth)

sub-section for the tradeoffs.

DC gain accuracy is usually limited by the tolerance of Rf

and Rg.

DC Gain (transimpedance)

Figure 3 shows a transimpedance circuit where the cur-

rent Iin is injected at the inverting node. The current

source’s output resistance is much greater than Rf.

The DC transimpedance gain is:

The recommended Rf is 453Ω. Parasitic capacitance at

the inverting node may require a slight increase of Rf to

maintain a flat frequency response.

DC gain accuracy is usually limited by the tolerance of Rf.

Figure 3: Transimpedance Gain

DC Design (level shifting)

Figure 4 shows a DC level shifting circuit for inverting

gain configurations. Vref produces a DC output level

shift of

, which is independent of the DC

output produced by Vin.

Figure 4: Level Shifting Circuit

DC Design (single supply)

Figure 5 is a typical single-supply circuit. R1 and R2 form

a voltage divider that sets the non-inverting input DC volt-

age. This circuit has a DC gain of 1. A low

frequency zero is set by Rg and C2. The coupling capac-

itor

C1 isolates its DC bias point from the

previous stage. Both capacitors make a high pass

response; high frequency gain is determined by Rf and Rg.

Figure 5: Single Supply Circuit

The complete gain equation for the circuit in Figure 5 is:

=−

CLC446

0.1

µF

6.8

µF

Vin

VCC

0.1

µF

6.8

µF

VEE

== −

CLC446

0.1

µF

6.8

µF

VCC

0.1

µF

6.8

µF

VEE

Iin

Vin

CLC446

Vref

Rref

CLC446

Vin

VCC

⋅

+⋅ +













−⋅

ref

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