IS62LV256

1

Rev. K

12/11/02

Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

• Access time: 45, 70 ns

• Low active power: 70 mW

• Low standby power

— 45 µW CMOS standby

• Fully static operation: no clock or refresh

required

• TTL compatible inputs and outputs

• Single 3.3V power supply

DESCRIPTION

The

32,768-word by 8-bit static RAM. It is fabricated using

high-performance CMOS double-metal technology.

When

CE is HIGH (deselected), the device assumes a

standby mode at which the power dissipation is reduced to

10 µW (typical) with CMOS input levels.

Easy memory expansion is provided by using an active LOW

Chip Enable (

CE) input and an active LOW Output Enable

(

OE) input. The active LOW Write Enable (WE) controls both

writing and reading of the memory.

The IS62LV256 is pin compatible with other 32K x 8 SRAMs

in 300-mil SOJ, 330-mil plastic SOP, and TSOP (Type I Normal

and Reverse Bent) packages.

32K x 8 LOW VOLTAGE STATIC RAM

FUNCTIONAL BLOCK DIAGRAM

A0-A14

CE

OE

WE

256 X 1024

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

DECEMBER 2002