SDIN

SDO

SCLK

SYNC

SDIN

SDO

SCLK

SYNC

SDIN

SDO

SCLK

SYNC

DACx0004

DACx0004

DACx0004

C

B

A

1

2

32

1

2

SCLK

SYNC

SDIN

32

X

DB31

DB0

DB31

DB0

DB31

DB0

SDO

Read Command

NOP Command

Readback Data

21

DAC80004, DAC70004, DAC60004

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SLASED6B – APRIL 2016 – REVISED JUNE 2016

Product Folder Links: DAC80004 DAC70004 DAC60004

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Copyright © 2016, Texas Instruments Incorporated

Device Functional Modes (continued)

8.4.1.1.2

Read-Back Mode

The READ command is used to start read-back operation. However, before read-back operation can be initiated,

the SDO pin must be enabled by setting the DSDO bit to '1'; this bit is disabled by default. Read-back operation

is then started by executing a READ command (R/W bit = '1', see Table 3). Bits C3 to C0 select the register to

be read. The remaining data in the command are don’t care bits. During the next SPI operation, the data

appearing on the SDO output are from the previously addressed register. For a read of a single register, a NOP

(No Operation) command (1110) can be used to clock out the data from the selected register on SDO. Multiple

registers can be read if multiple READ commands are issued (see Figure 54).

Figure 54. Read-Back Operation

8.4.1.2 Daisy-Chain Mode

For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices

together (see Figure 55). Daisy-chain operation can be useful in system diagnostics and in reducing the number

of serial interface lines. The daisy-chain feature can be enabled by writing a logic '1' to the DSDO bit (see

Table 3); the SDO pin is set to HIZ when the DSDO bit is set to 0.

The first falling edge of SYNC starts the operating cycle. SCLK is continuously applied to the SPI shift register

when SYNC is low. If more than 32 clock pulses are applied, the data ripples out of the shift register and appear

on the SDO line. The data bits are clocked out on the rising edge of SCLK and are valid on the falling edge. By

connecting the SDO pin of the first device to the SDI input of the next device in the chain, a multiple-device

interface is constructed (see Figure 2). Each device in the system requires 32 clock pulses. Therefore, the total

number of clock cycles must equal 32 × N, where N is the total number of DACx0004s in the chain. When the

serial transfer to all devices is complete, SYNC is taken high. This action latches the data from the SPI shift

registers to the device internal registers for each device in the daisy-chain and prevents any further data from

being clocked in. The serial clock can be a continuous or a gated clock. Note that a continuous SCLK source can

only be used if SYNC is held low for the correct number of clock cycles. For gated clock mode, a burst clock

containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock in

order to latch the data.

Figure 55. DACx0004 in Daisy Chain Mode

8.4.1.2.1

SYNC Interrupt – Daisy-Chain Mode

For daisy-chain operation, the SYNC line stays low for at least 32 × N SCLK cycles, where N is the number of

DACx0004s in the daisy chain. If SYNC is brought high before a multiple 32 SCLKs, it acts as an interrupt to the

write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer

contents, DAC register contents, nor a change in the operating mode occurs (see Figure 56).