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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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AD7997 Datenblatt(PDF) 18 Page - Analog Devices |
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AD7997 Datenblatt(HTML) 18 Page - Analog Devices |
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18 / 32 page  AD7997/AD7998 Rev. 0 | Page 18 of 32 INTERNAL REGISTER STRUCTURE The AD7997/AD7998 contain 17 internal registers that are used to store conversion results, high and low conversion limits, and information to configure and control the device (see Figure 25). Sixteen are data registers and one is an address pointer register. Each data register has an address that the address pointer register points to when communicating with it. The conversion result register is the only data register that is read only. ADDRESS POINTER REGISTER Because it is the register to which the first data byte of every write operation is written automatically, the address pointer register does not have and does not require an address. The address pointer register is an 8-bit register in which the 4 LSBs are used as pointer bits to store an address that points to one of the AD7997/AD7998’s data registers. The 4 MSBs are used as command bits when operating in Mode 2 (see the Modes of Operation section). The first byte following each write address is to the address pointer register, containing the address of one of the data registers. The 4 LSBs select the data register to which subsequent data bytes are written. Only the 4 LSBs of this register are used to select a data register. On power-up, the address pointer register contains all 0s, pointing to the conversion result register. Table 7. Address Pointer Register C4 C3 C2 C1 P3 P2 P1 P0 0 0 0 0 Register Select Table 8. AD7997/AD7998 Register Addresses P3 P2 P1 P0 Registers 0 0 0 0 Conversion Result Register (Read) 0 0 0 1 Alert Status Register (Read/Write) 0 0 1 0 Configuration Register (Read/Write) 0 0 1 1 Cycle Timer Register (Read/Write) 0 1 0 0 DATALOW Reg CH1 (Read/Write) 0 1 0 1 DATAHIGH Reg CH1 (Read/Write) 0 1 1 0 Hysteresis Reg CH1 (Read/Write) 0 1 1 1 DATALOW Reg CH2 (Read/Write) 1 0 0 0 DATAHIGH Reg CH2 (Read/Write) 1 0 0 1 Hysteresis Reg CH2 (Read/Write) 1 0 1 0 DATALOW Reg CH3 (Read/Write) 1 0 1 1 DATAHIGH Reg CH3 (Read/Write) 1 1 0 0 Hysteresis Reg CH3 (Read/Write) 1 1 0 1 DATALOW Reg CH4 (Read/Write) 1 1 1 0 DATAHIGH Reg CH4 (Read/Write) 1 1 1 1 Hysteresis Reg CH4 (Read/Write) CONFIGURATION REGISTER ADDRESS POINTER REGISTER SERIAL BUS INTERFACE SDA SCL D A T A DATALOW REGISTER CH2 DATAHIGH REGISTER CH2 DATALOW REGISTER CH1 HYSTERESIS REGISTER CH1 DATAHIGH REGISTER CH1 CYCLE TIMER REGISTER ALERT STATUS REGISTER CONVERSION RESULT REGISTER HYSTERESIS REGISTER CH2 DATAHIGH REGISTER CH3 DATALOW REGISTER CH3 HYSTERESIS REGISTER CH3 DATAHIGH REGISTER CH4 DATALOW REGISTER CH4 HYSTERESIS REGISTER CH4 Figure 25. AD7997/AD7998 Register Structure |
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