Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

AD7997 Datenblatt(PDF) 19 Page - Analog Devices

Teilenummer AD7997
Bauteilbeschribung  8-Channel, 10- and 12-Bit ADCs with I2CCompatible
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7997 Datenblatt(HTML) 19 Page - Analog Devices

Back Button AD7997 Datasheet HTML 15Page - Analog Devices AD7997 Datasheet HTML 16Page - Analog Devices AD7997 Datasheet HTML 17Page - Analog Devices AD7997 Datasheet HTML 18Page - Analog Devices AD7997 Datasheet HTML 19Page - Analog Devices AD7997 Datasheet HTML 20Page - Analog Devices AD7997 Datasheet HTML 21Page - Analog Devices AD7997 Datasheet HTML 22Page - Analog Devices AD7997 Datasheet HTML 23Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 19 / 32 page
background image
AD7997/AD7998
Rev. 0 | Page 19 of 32
CONFIGURATION REGISTER
The configuration register is a 16-bit read/write register that is used to set the operating mode of the AD7997/AD7998. The 4 MSBs of the
register are unused. The bit functions of all 12 LSBs of the configuration register are outlined in Table 9. A 2-byte write is necessary when
writing to the configuration register.
Table 9. Configuration Register Bits and Default Settings at Power-Up
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DONTC
DONTC
DONTC
DONTC
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
FLTR
ALERT
EN
BUSY/
ALERT
ALERT/BUSY
POLARITY
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Table 10. Bit Function Descriptions
Bit
Mnemonic
Comment
D11 to D4
CH8 to CH1
These 8-channel address bits select the analog input channel(s) to be converted. A 1 in any of Bits D11 to D4
selects a channel for conversion. If more than one channel bit is set to 1, the AD7997/AD7998 sequence
through the selected channels, starting with the lowest channel. All unused channels should be set to 0. Prior
to initiating a conversion, a channel or channels for conversion must be selected in the configuration register.
D3
FLTR
The value written to this bit of the control register determines whether the filtering on SDA and SCL is
enabled or is to be bypassed. If this bit is a 1, then the filtering is enabled; if it is a 0, the filtering is bypassed.
D2
ALERT EN
The hardware ALERT function is enabled if this bit is set to 1, and disabled if this bit is set to 0. This bit is used
in conjunction with the BUSY/ALERT bit to determine if the ALERT/BUSY pin acts as an ALERT or a BUSY
output (see Table 12).
D1
BUSY/ALERT
This bit is used in conjunction with the ALERT EN bit to determine if the ALERT/ BUSY output, Pin 17, acts as
an ALERT or BUSY output (see Table 12), and if Pin 17 is configured as an ALERT output pin, if it is to be reset.
D0
BUSY/ALERT
POLARITY
This bit determines the active polarity of the ALERT/BUSY pin regardless of whether it is configured as an
ALERT or BUSY output. It is active low if this bit is set to 0, and active high if set to 1.
Table 11. Channel Selection
D11
D10
D9
D8
D7
D6
D5
D4
Selected Analog Input Channel
Comments
0
0
0
0
0
0
0
1
Convert on Channel 1 (VIN1)
0
0
0
0
0
0
1
0
Convert on Channel 2 (VIN2)
0
0
0
0
0
1
0
0
Convert on Channel 3 (VIN3)
0
0
0
0
1
0
0
0
Convert on Channel 4 (VIN4)
0
0
0
1
0
0
0
0
Convert on Channel 5 (VIN5)
0
0
1
0
0
0
0
0
Convert on Channel 6 (VIN6)
0
1
0
0
0
0
0
0
Convert on Channel 7 (VIN7)
1
0
0
0
0
0
0
0
Convert on Channel 8 (VIN8)
If more than one channel is
selected, the AD7997/AD7998
start converting on the selected
sequence of channels starting with
the lowest channel in the
sequence.
Table 12. ALERT/BUSY Function
D2
D1
ALERT/BUSY Pin Configuration
0
0
Pin does not provide any interrupt signal.
0
1
Pin configured as a BUSY output.
1
0
Pin configured as an ALERT output.
1
1
Resets the ALERT output pin, the Alert_Flag bit in the conversion result register, and the entire alert status register
(if any is active). If 1/1 is written to Bits D2/D1 in the configuration register to reset the ALERT pin, the Alert_Flag bit,
and the alert status register, the contents of the configuration register read 1/0 for D2/D1, respectively, if read back.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


Datenblatt Download

Go To PDF Page


Link URL



War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Link zum Datenblatt    |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com