LPC2104 datasheet(8/32 Pages) PHILIPS

8 / 32 page

Philips Semiconductors

LPC2104/2105/2106

Single-chip 32-bit microcontrollers

Product data

Rev. 04 — 05 February 2004

8 of 32

9397 750 12792

Functional description

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and

related decode mechanism are much simpler than those of microprogrammed

Complex Instruction Set Computers. This simplicity results in a high instruction

throughput and impressive real-time interrupt response from a small and

cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory

systems can operate continuously. Typically, while one instruction is being executed,

its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

THUMB, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially,

the ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit THUMB set.

The THUMB set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because THUMB

code operates on the same 32-bit register set as ARM code.

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-Chip Flash program memory

The LPC2104, LPC2105 and LPC2106 incorporate a 128 kB Flash memory system.

This memory may be used for both code and data storage. Programming of the Flash

memory may be accomplished in several ways. It may be programmed In System via

the serial port. The application program may also erase and/or program the Flash

while the application is running, allowing a great degree of ﬂexibility for data storage

ﬁeld ﬁrmware upgrades, etc. When on-chip bootloader is used, 120 kB of Flash

memory is available for user code.

6.3 On-Chip static RAM

On-Chip static RAM may be used for code and/or data storage. The SRAM may be

accessed as 8-bits, 16-bits, and 32-bits. The LPC2104 provides a 16 kB static RAM,

the LPC2105 provides a 32 kB static RAM, and the LPC2106 provides a 64 kB static

RAM.

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