Reference Tables

TABLE I

Bit 15

Premix Modulus

0

d

1

1

d

10

TABLE II

Bit

Reference

Tuning Resolution

16

17

Frequency

d

1 Premix

d

10 Premix

0

0

10 kHz

10 kHz

1 kHz

0

1

125 kHz

125 kHz

125 kHz

1

0

25 kHz

25 kHz

25 kHz

1

1

100 kHz

100 kHz

10 kHz

TABLE III

Bit 18

Mode

0

Normal Operation

1

Production Test

Mode Only

The user should always load Bit 18 low

TABLE IV

Bit 19

Timer

0

Bit 24 Status

1

Bit 24 for 300 ms

TIMER OPERATION

The timer function is provided for use as a retriggerable

‘‘one shot’’ to enable muting for approximately 300 millisec-

onds after station changes The timer is enabled at bit 24’s

output if the normal operating mode is selected (shift regis-

latched as a ‘‘HI’’ The timer’s output state will invert imme-

diately upon latching bit 19 ‘‘HI’’ and remain inverted for

approximately 300 milliseconds If the user readdresses the

device with bit 19 data ‘‘LOW’’ before the timer finishes its

cycle the timer’s BIT 24 output will finish out the 300 ms

pulse Readdressing the device with bit 19 ‘‘HI’’ before the

timer finishes its cycle will extend the BIT 24 output pulse

width by 300 ms Addressing should be performed immedi-

ately after the 50 Hz output transitions ‘‘HI’’ BIT 24’s output

power up as a result of a timer reset in progress

TABLE V

Bit

FUNCTION OF

20

21

PINS 3 4

5

0

0

Status of Bits 22-24

0

1

Test mode 1

1

0

Test mode 2

1

1

Test mode 3

TEST MODE OPERATION

Test Mode 1

Enables the BIT output pins to edge trigger

the phase comparator inputs and monitor an internal lock

detector BIT 22 negative edge triggers the reference divid-

er input of the phase comparator if the reference divider

state is low BIT 23 provides the open collector ORing of the

phase comparator’s pump up and down outputs BIT 24

negative edge triggers the N counter input of the phase

comparator if the N counter state is preconditioned low

Test Mode 2

Enables the BIT outputs to clock the pro-

grammable N counter monitor its output and force either its

load or count condition BIT 22 provides the N counter out-

put which negative edge triggers the phase comparator and

which appears low one N counter clock pulse before it re-

loads BIT 23 positive edge triggers the N counter’s clock

input if the prescaler’s output is preconditioned HI BIT 24

clears the N counter output so that loading will occur on the

next N counter clock edge

Test Mode 3

Enables the BIT outputs to clock the 50 Hz

and 10 kHz reference dividers and monitor the reference

divider input to the phase comparator BIT 22 positive edge

clocks the 10 kHz reference divider chain if the 10 kHz out-

put is preconditioned HI BIT 23 positive edge clocks the 50

Hz divider chain BIT 24 is the reference divider negative

edge trigger input to the phase comparator

3