PCM3500ESLASH2K datasheet(13/26 Pages) TI

13 / 26 page

PCM3500

Reset and Power Down

The PCM3500 supports power-on reset, external reset, and

power-down operations. Power-on reset is performed by

internal circuitry automatically at power up, while the exter-

nal reset is initiated using the PDWN input (pin 20).

Power-on reset occurs when power and system clock are

initially applied to the PCM3500. The internal reset cir-

cuitry requires that the system clock be active at power up,

with at least three system clock cycles occurring prior to

VDD = 2.2V. When VDD exceeds 2.2V, the power-on reset

comparator enables the initialization sequence, which re-

quires 1024 system clock periods for completion. During

the initialization sequence, the DAC output is forced to

AGND, and the ADC output is forced to a high impedance

state. After the initialization sequence has completed, the

DAC and ADC outputs experience a delay before they

output a valid signal or data. Refer to Figures 3 and 5 for

power-on reset and post-reset delay timing.

External reset is performed by first setting PDWN = ‘0’ and

then setting PDWN = ‘1’. The LOW to HIGH transition on

PDWN causes the reset initialization sequence to start.

During the initialization sequence, the DAC output is forced

to AGND, and the ADC output is forced to a high impedance

state. After the initialization sequence has completed, the

DAC and ADC outputs experience a delay before they

output a valid signal or data. Refer to Figures 4 and 5 for

external reset and post-reset delay timing.

Power-down mode is enabled by setting PDWN = ‘0’.

During power-down mode, minimum current is drawn when

the system clock is removed, resulting in 60

µA (typical)

power supply current. The PDWN input includes an internal

pull-down resistor, which places the PCM3500 in power-

down mode at power-up if the PDWN pin is left uncon-

nected. Ideally, the PDWN input should be driven by active

logic in order to control reset and power-down operation. If

the PDWN pin is to be unused in the system application, it

should be connected to VDD to enable normal operation. By

setting PDWN = ‘1’ when exiting power-down mode, the

PCM3500 will initiate an external reset as described earlier

in this section.

1024 System Clock Periods

Reset

Reset Removal

2.4V

2.2V

2.0V

Internal Reset

System Clock

FIGURE 3. Power-On Reset Timing.

1024 System Clock Periods

Reset

Reset Removal

System Clock

Internal Reset

PDWN

RST

PWDN = LOW Pulse Width

RST = 40ns minimum

FIGURE 4. External Reset Timing.

FIGURE 5. DAC and ADC Output for Reset and Power Down.

Reset

Power Down

GND

COM

(0.5V

CC)

Ready/Operation

Internal Reset

or Power Down

ADC DOUT

DAC V

OUT

High Impedance

(1)

ADCDLY1 (2304/fS)

DACDLY1 (2048/fS)

Reset Removal or Power Down OFF

NOTE: (1) The HPF transient response (exponentially attenuated signal from

±0.2% DC of FSR with 200ms time constant) appears initially.

PCM3500E/2K Datenblatt(PDF) 13 Page - Texas Instruments

PCM3500E/2K Datenblatt(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datenblatt Download

Link URL