DF1706

6

SBAS182

SYSTEM CLOCK REQUIREMENTS

The system clock of the DF1706 can be supplied by either an

external clock signal at XTI (pin 6), or by the on-chip crystal

DF1706, the Over-Sampling Ratio (OSR) of the DF1706's

digital filter should be four times instead of eight times. The

OSR can be selected by the x4 pin (pin 21) in hardware mode

or x4 bit on MODE 2 register in software mode.

the on-chip crystal oscillator is limited to a maximum fre-

quency of 24.0MHz. Table I shows the typical system clock

frequencies for selected sample rates.

The DF1706 includes a system clock detection circuit that

determines the system clock rate in use. The circuit compares

the system clock input (XTI) frequency with the LRCIN input

rate to determine the system clock multiplier. Ideally, LRCIN

and BCKIN should be derived from the system clock to

ensure proper synchronization. If the phase difference be-

tween the system clock and LRCIN is larger than

±4 bit clock

(BCKIN) periods, the synchronization of the system and

LRCIN clocks will be performed automatically by the DF1706.

Timing requirements for the system clock input are shown in

Figure 1.

SYSTEM CLOCK FREQUENCY (MHz)

32kHz

N/A

N/A

8.192

12.288

16.384

44.1kHz

N/A

N/A

11.2896

16.934

22.5792

48kHz

N/A

N/A

12.288

18.432

88.2kHz

N/A

N/A

N/A

N/A

96kHz

N/A

N/A

24.576

N/A

N/A

176.4kHz

N/A

N/A

N/A

N/A

192kHz

N/A

N/A

N/A

N/A

NOTES: (1) Crystal oscillator frequency using internal oscillator is not covered at frequency larger than 24.0MHz. (2) x4 (pin 21) should be set to HIGH.

TABLE I. Typical System Clock Frequencies.

FIGURE 1. System Clock Timing.

RESET

The DF1706 has both an internal power-on reset circuit and

a reset pin, RST (pin 14), for providing an external reset

signal. The internal power-on reset is performed automati-

cally when power is applied to the DF1706, as shown in

Figure 2. The RST pin can be used to synchronize the

DF1706 with a system reset signal, as shown in Figure 3.

During the power-on reset period (1024 system clocks), the

outputs of BCKO, DOL, and DOR are forced LOW and the

output of WCKO is forced HIGH. For an external forced reset,

the outputs of BCKO, DOL, and DOR are forced LOW and the

output of WCKO is forced HIGH during the initialization

period (1024 system clocks), which occurs after the LOW-to-

HIGH transition of the RST pin (see Figure 3).

1024 system clocks

Reset

Reset Removal

2.8V

1.8V

Internal Reset

System Clock

FIGURE 2. Internal Power-On Reset Timing.

t

SCKH

t

SCKL

2.0V

0.8V

HIGH

LOW

System Clock

NOTE: (1) For f

t

For f

t

SYMBOL

PARAMETERS

MIN

MAX

UNITS

t

SCKH

12

t

SCKL

System Clock Pulse Width LOW

12