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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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DF1706E/2K Datenblatt(PDF) 11 Page - Texas Instruments |
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DF1706E/2K Datenblatt(HTML) 11 Page - Texas Instruments |
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11 / 16 page  DF1706 11 SBAS182 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 MODE0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 MODE1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 MODE2 res res res res res A1 A0 res res OW1 OW0 IW1 IW0 x4 DEM MUT MODE3 res res res res res A1 A0 res SF1 SF0 CKO res SRO ATC LRP I2S B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 ML MC MD FIGURE 8. Internal Mode Control Registers. FIGURE 9. Software Interface Format. REGISTER BIT NAME NAME DESCRIPTION MODE0 AL[7:0] Attenuation Data for the Left Channel LDL Attenuation Load Control for the Left Channel A[1:0] Register Address res Reserved MODE1 AR[7:0] Attenuation Data for the Right Channel LDL Attenuation Load Control for the Right Channel A[1:0] Register Address res Reserved MODE2 MUT Soft Mute Control DEM Digital De-Emphasis Control x4 Oversampling Rate Control IW[1:0] Input Data Format and Word Length OW[1:0] Output Data Word Length A[1:0] Register Address res Reserved MODE3 I2S Input Data Format (I2S or Standard/Left-Justified) LRP LRCIN Polarity ATC Attenuator Control, Dependent or Independent SRO Digital Filter Roll-Off Selection (sharp or slow) CKO CLKO Frequency Selection (XTI or XTI ÷ 2) SF[1:0] Sample Rate Selection for De-Emphasis Function A[1:0] Register Address res Reserved NOTE: All reserved bits should be programmed to 0. TABLE V. Internal Register Mapping. A1 A0 REGISTER SELECTED 0 0 MODE0 0 1 MODE1 1 0 MODE2 1 1 MODE3 TABLE VI. Internal Register Addressing. 0.5V DD 0.5V DD 0.5V DD ML(1) MC(2) MD NOTES: (1) ML rising edge to the next MC rising edge. (2) MC rising edge for LSB to ML rising edge. t MLH t MHH t MCH t MCL t MDS t MCY t MLS t MLL t MDH LSB MC Pulse Cycle Time MC Pulse Width LOW MC Pulse Width HIGH MD Hold Time MD Set-Up Time ML LOW Level Time ML HIGH Level Time ML Hold Time(1) ML Set-Up Time(2) t MCY t MCL t MCH t MDH t MDS t MLL t MHH t MLH t MLS 100ns (min) 40ns (min) 40ns (min) 10ns (min) 10ns (min) 40ns 40ns 20ns (min) 20ns (min) FIGURE 10. Software Interface Timing Requirements. |
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