VPC3232D datasheet(70/78 Pages) MICRONAS

70 / 78 page

VPC 323xD, VPC 324xD

ADVANCE INFORMATION

Micronas

4.6.4.12. Characteristics, Clock Output Specification

Line-Locked Clock Pins: LLC1, LLC2

Fig. 4–18: Line-locked clock output pins

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Load capacitance

–

13.5 MHz Line Locked Clock

1/T13

LLC1 Clock Frequency

12.5

–

14.5

MHz

tWL13

LLC1 Clock Low Time

–

CL = 30 pF

tWH13

LLC1 Clock High Time

–

CL = 30 pF

1/T27

LLC2 Clock Frequency

–

MHz

tWL27

LLC2 Clock Low Time

–

CL = 30 pF

tWH27

LLC2 Clock High Time

–

CL = 30 pF

16 MHz Line Locked Clock

1/T13

LLC1 Clock Frequency

14.8

–

17.2

MHz

18 MHz Line Locked Clock

1/T13

LLC1 Clock Frequency

16.6

–

19.4

MHz

common timings – all modes

tSK

Clock Skew

–

tR, tF

Clock Rise/Fall TimeClock

–

LLC1=13.5MHz, CL = 30 pF

tR, tF

Clock Rise/Fall TimeClock

–

LLC2=27.0MHz, CL = 30 pF

VIL

Input Low Voltage

–

0.8

VIH

Input High Voltage

2.0

–

VOL

Output Low Voltage

–

0.4

IL = 2 mA

VOH

Output High Voltage

2.4

–

IH = –2 mA

(13.5 MHz

±7%)

(27 MHz

±7%)

LLC2

LLC1

VIL

VIH

VIL

VIH

tSK

tWL13

tWH13

T13

T27

tWL27

tWH27

tSK

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