VPC3232D datasheet(18/78 Pages) MICRONAS

18 / 78 page

VPC 323xD, VPC 324xD

ADVANCE INFORMATION

Micronas

2.9.2. Sync Signals

The front end will provide a number of sync/control sig-

nals which are output with the output clock. The sync

signals are generated in the line-locked clock block.

– Href:

horizontal sync

– AVO:

active video out (programmable)

– HC:

horizontal clamp (programmable)

– Vref:

vertical sync

– INTLC:

interlace

All horizontal signals are not qualified with field infor-

mation, i.e. the signals are present on all lines. The

horizontal timing is shown in Fig. 2–16. Details of the

horizontal/vertical timing are given in Fig. 2–20.

Note: In the ITU-R656 compliant output format, the

sync information is embedded in the data stream.

2.9.3. DIGIT3000 Output Format

The picture bus format between all DIGIT3000 ICs is

4:2:2 YCrCb with 20.25 MHz samples/s. Only active

video is transferred, synchronized by the system main

sync signal (MSY) which indicates the start of valid

data for each scan line and which initializes the color

multiplex. The video data is orthogonally sampled

YCrCb, the output format is given in Table 2–4. The

number of active samples per line is 1080 for all stan-

dards (525 and 625).

The output can be switched to 4:1:1 mode with the out-

put format according to Table 2–5.

Via the MSY line, serial data is transferred which con-

tains information about the main picture such as cur-

rent line number, odd/even field etc.). It is generated by

the deflection circuitry and represents the orthogonal

timebase for the entire system.

2.9.4. Line-Locked 4:2:2 Output Format

In line-locked mode, the VPC 32xx will produce the

industry standard pixel stream for YCrCb data. The dif-

ference to DIGIT3000 native mode is only the number

of active samples, which of course, depends on the

chosen scaling factor. Thus, Table 2–4 is valid for both

4:2:2 modes.

2.9.5. Line-Locked 4:1:1 Output Format

The orthogonal 4:1:1 output format is compatible to the

industry standard. The YCrCb samples are skew-cor-

rected and interpolated to an orthogonal sampling ras-

ter (see Table 2–5).

note: C*x

(x = pixel number and y = bit number)

2.9.6. ITU-R 656 Output Format

This interface uses a YCrCb 4:2:2 data stream at a

line-locked clock of 13.5 MHz. Luminance and chromi-

nance information is multiplexed to 27 MHz in the fol-

lowing order:

Cb1, Y1, Cr1, Y2, ...

Timing reference codes are inserted into the data

stream at the beginning and the end of each video line:

– a ‘Start of active video’-Header (SAV) is inserted

before the first active video sample

– a ‘End of active video’-code (EAV) is inserted after

the last active video sample.

The incoming videostream is limited to a range of

1...254 since the data words 0 and 255 are used for

identification of the reference headers. Both headers

contain information about the field type and field blank-

ing. The data words occurring during the horizontal

blanking interval between EAV and SAV are filled with

0x10 for luminance and 0x80 for chrominance informa-

tion. Table 2–6 shows the format of the SAV and EAV

header.

For activation of this output format, the following selec-

tions must be assured:

– 13.5 MHz line locked clock

– double-clock mode enabled

– ITU-R656-mode enabled

– binary offset for Cr/Cb data

Note that the following changes and extensions to the

ITU-R656 standard have been included to support hor-

izontal and vertical scaling:

Table 2–4: Orthogonal 4:2:2 output format

Luma

Chroma

Cb1

Cr1

Cb3

Cr3

Table 2–5: 4:1:1 Orthogonal output format

Luma

Chroma

C3, C7

C2, C6

C1, C5

C0, C4

Cb1

Cr1

Cb1

Cr1

Cb1

Cr1

Cb1

Cr1

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