ADS1251 datasheet(11/17 Pages) TI

11 / 17 page

ADS1251

SBAS184A

www.ti.com

is HIGH prior to the internal transfer of new data to the DOR.

The result of the A/D conversion is written to the DOR from

the Most Significant Bit (MSB) to the Least Significant Bit

(LSB) in the time defined by t1 (see Figures 11 and 12). The

DOUT/DRDY line then pulses LOW for the time defined by

t2, and then pulses HIGH for the time defined by t3 to indicate

that new data is available to be read. At this point, the

function of the DOUT/DRDY pin changes to DOUT mode.

Data is shifted out on the pin after t7. The device communi-

cating with the ADS1251 can provide SCLKs to the ADS1251

after the time defined by t6. The normal mode of reading data

from the ADS1251 is for the device reading the ADS1251 to

latch the data on the rising edge of SCLK (because data is

shifted out of the ADS1251 on the falling edge of SCLK). In

order to retrieve valid data, the entire DOR must be read

before the DOUT/DRDY pin reverts back to DRDY mode.

If SCLKs are not provided to the ADS1251 during the DOUT

mode, the MSB of the DOR is present on the DOUT/DRDY

line until the time defined by t4. If an incomplete read of the

ADS1251 takes place while in DOUT mode (that is, less than

24 SCLKs were provided), the state of the last bit read is

present on the DOUT/DRDY line until the time defined by t4.

If more than 24 SCLKs are provided during DOUT mode, the

DOUT/DRDY line stays LOW until the time defined by t4.

The internal data pointer for shifting data out on DOUT/DRDY

is reset on the falling edge of the time defined by t1 and t4.

This ensures that the first bit of data shifted out of the

ADS1251 after DRDY mode is always the MSB of new data.

SYNCHRONIZING MULTIPLE CONVERTERS

The normal state of SCLK is LOW; however, by holding SCLK

HIGH, multiple ADS1251s can be synchronized. This is accom-

plished by holding SCLK HIGH for at least four, but less than 20,

consecutive DOUT/DRDY cycles (see Figure 13). After the

ADS1251 circuitry detects that SCLK has been held HIGH for

four consecutive DOUT/DRDY cycles, the DOUT/DRDY pin

pulses LOW for one CLK cycle and then is held HIGH, and the

modulator is held in a reset state. The modulator will be

released from reset and synchronization occurs on the falling

edge of SCLK. With multiple converters, the falling edge tran-

sition of SCLK must occur simultaneously on all devices. It is

important to note that prior to synchronization, the DOUT/DRDY

pulse of multiple ADS1251s in the system could have a differ-

ence in timing up to one DRDY period. Therefore, to ensure

synchronization, the SCLK must be held HIGH for at least five

DRDY cycles. The first DOUT/DRDY pulse after the falling

edge of SCLK occurs at t14. The first DOUT/DRDY pulse

indicates valid data.

FIGURE 9. Expanded Digital Filter Response (60Hz with a

60Hz data output rate).

FIGURE 10. Expanded Digital Filter Response (60Hz with a

10Hz data output rate).

DIGITAL FILTER RESPONSE

–20

–40

–60

–80

–100

–120

–140

–160

–180

–200

Frequency (Hz)

DIGITAL FILTER RESPONSE

–20

–40

–60

–80

–100

–120

–140

–160

–180

–200

Frequency (Hz)

ADS1251 Datenblatt(PDF) 11 Page - Texas Instruments

ADS1251 Datenblatt(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Datenblatt Download

Link URL