ADS1251 datasheet(12/17 Pages) TI

12 / 17 page

ADS1251

SBAS184A

www.ti.com

POWER-DOWN MODE

The normal state of SCLK is LOW; however, by holding

SCLK HIGH, the ADS1251 will enter power-down mode. This

is accomplished by holding SCLK HIGH for at least 20

consecutive DOUT/DRDY periods (see Figure 14). After the

ADS1251 circuitry detects that SCLK has been held HIGH for

four consecutive DOUT/DRDY cycles, the DOUT/DRDY pin

pulses LOW for one CLK cycle and then is held HIGH, and

the modulator is held in a reset state. If SCLK is held HIGH

for an additional 16 DOUT/DRDY periods, the ADS1251

enters power-down mode. The part will be released from

power-down mode on the falling edge of SCLK. It is impor-

tant to note that the DOUT/DRDY pin is held HIGH after four

DOUT/DRDY cycles, but power-down mode is not entered

for an additional 16 DOUT/DRDY periods. The first

DOUT/DRDY pulse after the falling edge of SCLK occurs at

t16 and indicates valid data. Subsequent DOUT/DRDY pulses

will occur normally.

SERIAL INTERFACE

The ADS1251 includes a simple serial interface which can be

connected to microcontrollers and digital signal processors in

a variety of ways. Communications with the ADS1251 can

commence on the first detection of the DOUT/DRDY pulse

after power up.

It is important to note that the data from the ADS1251 is a

24-bit result transmitted MSB-first in Offset Binary Two’s

Complement format, as shown in Table III.

The data must be clocked out before the ADS1251 enters

DRDY mode to ensure reception of valid data, as described

in the DOUT/DRDY section of this data sheet.

TABLE III. ADS1251 Data Format (Offset Binary Two’s

Complement).

DIFFERENTIAL VOLTAGE INPUT

DIGITAL OUTPUT (HEX)

+Full-Scale

7FFFFFH

Zero

000000H

–Full-Scale

800000H

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tDRDY

Conversion Cycle

384 • CLK

DRDY Mode

36 • CLK

DOUT Mode

348 • CLK

DOR Write Time

6 • CLK

DOUT/DRDY LOW Time

6 • CLK

DOUT/DRDY HIGH Time (Prior to Data Out)

6 • CLK

DOUT/DRDY HIGH Time (Prior to Data Ready)

24 • CLK

Rising Edge of CLK to Falling Edge of DOUT/DRDY

End of DRDY Mode to Rising Edge of First SCLK

End of DRDY Mode to Data Valid (Propagation Delay)

Falling Edge of SCLK to Data Valid (Hold Time)

Falling Edge of SCLK to Next Data Out Valid (Propagation Delay)

t10

SCLK Setup Time for Synchronization or Power Down

t11

DOUT/DRDY Pulse for Synchronization or Power Down

1 • CLK

t12

Rising Edge of SCLK Until Start of Synchronization

1537 • CLK

7679 • CLK

t13

Synchronization Time

0.5 • CLK

6143.5 • CLK

t14

Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode

2042.5 • CLK

t15

Rising Edge of SCLK Until Start of Power Down

7681 • CLK

t16

Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode

2318.5 • CLK

t17

Falling Edge of Last DOUT/DRDY to Start of Power Down

6144.5 • CLK

TABLE II. Digital Timing.

FIGURE 11. DOUT/DRDY Partitioning.

DATA

DRDY Mode

DOUT Mode

DATA

DRDY Mode

DOUT/DRDY

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