CHA6550-QXG

Ref. : DSCHA6550-QXG6159 - 07 Jun 16

4/18

Specifications subject to change without notice

Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France

Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 - www.ums-gaas.com

Device thermal performances

All the figures given in this section are obtained assuming that the QFN device is only cooled

down by conduction through the package thermal pad (no convection mode considered).

The temperature is monitored at the package back-side interface (Tcase).

The system maximum temperature must be adjusted in order to guarantee that Tjunction

remains below the maximum value specified in the Absolute Maximum Ratings table.

So, the system PCB must be designed to comply with this requirement.

Parameter

Biasing

conditions

Tjunction

(°C)

( °C/W)

T50

( hours)

(1)

Thermal Resistance

( Junction to Case)

Vd= 6V

Id= 1300mA

Pdiss= 7.8W

176

11.8

3.0E+07

(1) Assuming 85°C Tcase

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

100

120

140

160

180

200

220

240

Junction Temperature (°C)