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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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DS2156 Datenblatt(PDF) 1 Page - Dallas Semiconductor |
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DS2156 Datenblatt(HTML) 1 Page - Dallas Semiconductor |
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1 / 262 page  1 of 262 110502 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here:www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS2156 is a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and long-haul applications. The backplane is user- configurable for a TDM or UTOPIA II bus interface. The DS2156 is composed of a line interface unit (LIU), framer, HDLC controllers, and a UTOPIA/TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS2156 is pin and software compatible with the DS2155. The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line buildouts as well as CSU line buildouts of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock and data from the network. APPLICATIONS Inverse Mux ATM (IMA) T1/E1/J1 Line Cards Switches and Routers Add-Drop Multiplexers FEATURES § Complete T1/DS1/ISDN-PRI/J1 Transceiver Functionality § Complete E1 (CEPT) PCM-30/ISDN-PRI Transceiver Functionality § User-Selectable TDM or UTOPIA II Bus Interface § Long-Haul and Short-Haul Line Interface for Clock/Data Recovery and Waveshaping § CMI Coder/Decoder for Optical I/F § Crystal-Less Jitter Attenuator § Fully Independent Transmit and Receive Functionality § Dual HDLC Controllers § Programmable BERT Generator and Detector § Internal Software-Selectable Receive and Transmit-Side Termination Resistors for 75Ω/100Ω/120Ω T1 and E1 Interfaces § Dual Two-Frame Elastic-Store Slip Buffers that Connect to Asynchronous Backplanes Up to 16.384MHz § 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz Clock Output Synthesized to Recovered Network Clock Features continued on page 8. ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE DS2156L 0°C to +70°C 100 LQFP DS2156LN -40°C to +85°C 100 LQFP DS2156 T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface www.maxim-ic.com DS2156 T1/E1/J1 TDM/UTOPIA T1/E1/J1 NETWORK BACKPLANE UTOPIA TDM |
Ähnliche Teilenummer - DS2156 |
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Ähnliche Beschreibung - DS2156 |
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