DS2156 datasheet(49/262 Pages) DALLAS

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DS2156

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6.2

Interrupt Handling

Various alarms, conditions, and events in the DS2156 can cause interrupts. For simplicity, these are all

referred to as events in this explanation. All status registers can be programmed to produce interrupts.

Each status register has an associated interrupt mask register. For example, SR1 (status register 1) has an

interrupt control register called IMR1 (interrupt mask register 1). Status registers are the only sources of

interrupts in the DS2156. On power-up, all writeable registers are automatically cleared. Since bits in the

IMRx registers have to be set = 1 to allow a particular event to cause an interrupt, no interrupts can occur

until the host selects which events are to product interrupts. Since there are potentially many sources of

interrupts on the DS2156, several features are available to help sort out and identify which event is

causing an interrupt. When an interrupt occurs, the host should first read the IIR1 and IIR2 registers

(interrupt information registers) to identify which status register (or registers) is producing the interrupt.

Once that is determined, the individual status register or registers can be examined to determine the exact

source. In multiple port configurations, two to eight DS2156s can be connected together by the 3-wire

ESIB feature. This allows multiple DS2156s to be interrogated by a single CPU port read cycle. The host

can determine the synchronization status, or interrupt status of up to eight devices with a single read. The

ESIB feature also allows the user to select from various events to be examined through this method. For

more information, see Section 29.

The U_RSR register in the UTOPIA sections works slightly different than all other status registers. Only

two of the bits in this register are capable of generating interrupts, U_RSR.0 and U_RSR.1. These two

bits, unlike the other status register bits, are only set if the corresponding mask bits U_RCR2.3 and

U_RCR2.4 are set.

Once an interrupt has occurred, the interrupt handler routine should set the INTDIS bit (CCR3.6) to stop

further activity on the interrupt pin. After all interrupts have been determined and processed, the interrupt

hander routine should re-enable interrupts by setting the INTDIS bit = 0.

6.3

Status Registers

When a particular event or condition has occurred (or is still occurring in the case of conditions), the

appropriate bit in a status register is set to a 1. All of the status registers operate in a latched fashion. This

means that if an event or condition occurs a bit is set to a 1. It remains set until the user reads that bit. An

event bit is cleared when it is read and it is not set again until the event has occurred again. Condition bits

such as RBL, RLOS, etc., remain set if the alarm is still present.

The user always proceeds a read of any of the status registers with a write. The byte written to the register

informs the DS2156 which bits the user wishes to read and have cleared. The user writes a byte to one of

these registers, with a 1 in the bit positions the user wishes to read and a 0 in the bit positions the user

does not wish to obtain the latest information on. When a 1 is written to a bit location, the read register is

updated with the latest information. When a 0 is written to a bit position, the read register is not updated

and the previous value is held. A write to the status registers is immediately followed by a read of the

same register. This write-read scheme allows an external microcontroller or microprocessor to

individually poll certain bits without disturbing the other bits in the register. This operation is key in

controlling the DS2156 with higher order languages.

Status register bits are divided into two groups, condition bits and event bits. Condition bits are typically

network conditions such as loss-of-sync or all-ones detect. Event bits are typically markers such as the

one-second timer, elastic store slip, etc. Each status register bit is labeled as a condition or event bit.

Some of the status registers have bits for both the detection of a condition and the clearance of the

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