CS8411 datasheet(23/38 Pages) CIRRUS

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CS8411 CS8412

DS61F1

CS8412 DESCRIPTION

The CS8412 does not need a microprocessor to

handle the non-audio data (although a micro may

be used with the C and U serial ports). Instead, ded-

icated pins are available for the most important

channel status bits. The CS8412 is a monolithic

CMOS circuit that receives and decodes digital au-

dio data which was encoded according to the digital

audio interface standards. It contains an RS422 line

receiver and clock and data recovery utilizing an

on-chip phase-locked loop. The audio data is out-

put through a configurable serial port that supports

14 formats. The channel status and user data have

their own serial pins and the validity flag is OR’ed

with the ERF flag to provide a single pin, VERF,

indicating that the audio output may not be valid.

This pin may be used by interpolation filters that

provide error correction. A block diagram of the

CS8412 is illustrated in Figure 16.

The line receiver and jitter performance are de-

scribed in the sections directly preceding the

CS8411 sections in the beginning of this data sheet.

Audio Serial Port

The audio serial port is used primarily to output au-

dio data and consists of three pins: SCK, FSYNC,

and SDATA. These pins are configured via four

control pins: M0, M1, M2, and M3. M3 selects be-

tween eight normal serial formats (M3 = 0), and six

special formats (M3 = 1).

Normal Modes (M3 = 0)

When M3 is low, the normal serial port formats

shown in Figure 17 are selected using M2, M1, and

M0. These formats are also listed in Table 3,

VA+

FILT

AGND

MCK

SDATA

SCK

FSYNC

De-Multiplexer

Audio

Serial

Port

CRC

check

RXP

RXN

VD+

DGND

Parity

Check

Frequency

Comparator

Error

Encoder

Channel

Status

Latch

Ca/

C0/

Ce/

Cd/

Cc/

Cb/

Multiplexer

Bi-phase

Decoder

and

Frame

Sync

Timing

VERF

CBL

ERF

SEL

CS12/

FCK

654

18 24

Clock & Data

Recovery

Figure 16. CS8412 Block Diagram

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