LM26 datasheet(13/20 Pages) NSC

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Operation Descriptions

SOFT START

The ON/SS1 pin has dual functionality as both channel

enable and soft start control. The soft start block diagram is

shown in Figure 3.

The LM2642 will remain in shutdown mode while both soft

start pins are grounded.In a normal application (with a soft

start capacitor connected between the ON/SS1 pin and

SGND) soft start functions as follows. As the input voltage

rises (note: Iss starts to flow when VIN

≥ 2.2V), the internal

5V LDO starts up, and an internal 2µA current charges the

soft start capacitor. During soft start phase, the error ampli-

fier output voltage at the COMPx pin is clamped at 0.55V

and the duty cycle is controlled only by the soft start voltage.

As the SSx pin voltage ramps up, the duty cycle increases

proportional to the soft start ramp, causing the output voltage

to ramp up. The rate at which the duty cycle increases

depends on the capacitance of the soft start capacitor. The

higher the capacitance, the slower the output voltage ramps

up. When the corresponding output voltage exceeds 98%

(typical) of the set target voltage, the regulator switches from

soft start to normal operating mode. At this time, the 0.55V

clamp at the output of the error amplifier releases and peak

current feedback control takes over. Once in peak current

feedback control mode, the output of the error amplifier will

travel within the 0.5V and 2V window to achieve PWM

control. See Figure 4.

During soft start, over-voltage protection and current limit

remain in effect. The under voltage protection feature is

activated when the ON/SS pin exceeds the timeout thresh-

old (3.3V typical). If the ON/SSx capacitor is too small, the

duty cycle may increase too rapidly, causing the device to

latch off due to output voltage overshoot above the OVP

threshold. This becomes more likely in applications requiring

low output voltage, high input voltage and light load. A

capacitance of 10nF is recommended at each soft start pin

to provide a smooth monotonic output ramp.

SEQUENTIAL STARTUP

Sequential startup can be implemented by simply connecting

PGOOD1 to SS/ON2. Once channel 1 has reached 94% of

nominal, PGOOD1 will go high, thus enabling SS/ON2. In

this mode of operation, channel 2 will be controlled by the

state of channel 1. If channel 1 falls out of the PGOOD1

window, channel 2 will be switched off immediately.

OVER VOLTAGE PROTECTION (OVP)

If the output voltage on either channel rises above 113% of

nominal, over voltage protection activates. Both channels

will latch off, and the PGOOD1 pin will go low. When the

OVP latch is set, the high side FET driver, HDRVx, is imme-

diately turned off and the low side FET driver, LDRVx, is

turned on to discharge the output capacitor through the

inductor. To reset the OVP latch, either the input voltage

must be cycled, or both channels must be switched off.

UNDER VOLTAGE PROTECTION (UVP) AND UV DELAY

If the output voltage on either channel falls below 80% of

nominal, under voltage protection activates. As shown in

Figure 5, an under-voltage event will shut off the UV_DELAY

MOSFET, which will allow the UV_DELAY capacitor to

charge at 5uA (typical). At the UV_DELAY threshold (2.3V

20046206

FIGURE 3. Soft Start and ON/OFF

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FIGURE 4. Voltage Clamp at COMPx Pin

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FIGURE 5. PGOOD, OVP and UVP

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