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The output voltage is limited by the maximum duty cycle as

well as the minimum on time. Figure 9 shows the limits for

input and output voltages. The recommended maximum out-

put voltage is approximately 1V less than the nominal input

voltage. At 30V input, the minimum output is approximately

2.3V and the maximum is approximately 27V.

For input voltages below 5.5V, VLIN5 must be connected to

Vin through a small resistor (approximately 4.7 ohm). This

will ensure that VLIN5 does not fall below the UVLO thresh-

old.

Output Capacitor Selection

In applications that exhibit large and fast load current

swings, the slew rate of such a load current transient may be

beyond the response speed of the regulator. Therefore, to

meet voltage transient requirements during worst-case load

transients, special consideration should be given to output

capacitor selection. The total combined ESR of the output

capacitors must be lower than a certain value, while the total

capacitance must be greater than a certain value. Also, in

applications where the specification of output voltage regu-

lation is tight and ripple voltage must be low, starting from the

required output voltage ripple will often result in fewer design

iterations.

ALLOWED TRANSIENT VOLTAGE EXCURSION

The allowed output voltage excursion during a load transient

(

∆Vc_s) is:

Where ±

δ% is the output voltage regulation window and

±e% is the output voltage initial accuracy.

Example: Vnom = 5V,

δ% = 7%, e% = 3.4%, Vrip = 40mV

peak to peak.

Since the ripple voltage is included in the calculation of

∆Vc_s, the inductor ripple current should not be included in

the worst-case load current excursion. That is, the worst-

case load current excursion should be simply maximum load

current change specification,

∆Ic_s.

MAXIMUM ESR CALCULATION

Unless the rise and fall times of a load transient are slower

than the response speed of the control loop, if the total

combined ESR (Re) is too high, the load transient require-

ment will not be met, no matter how large the capacitance.

The maximum allowed total combined ESR is:

Example:

∆Vc_s = 160mV, ∆Ic_s = 3A. Then Re_max =

53.3m

Ω.

Maximum ESR criterion can be used when the associated

capacitance is high enough, otherwise more capacitors than

the number determined by this criterion should be used in

parallel.

MINIMUM CAPACITANCE CALCULATION

In a switch mode power supply, the minimum output capaci-

tance is typically dictated by the load transient requirement.

If there is not enough capacitance, the output voltage excur-

sion will exceed the maximum allowed value even if the

maximum ESR requirement is met. The worst-case load

transient is an unloading transient that happens when the

input voltage is the highest and when the present switching

cycle has just finished. The corresponding minimum capaci-

tance is calculated as follows:

Notice it is already assumed the total ESR, Re, is no greater

than Re_max, otherwise the term under the square root will

be a negative value. Also, it is assumed that L has already

been selected, therefore the minimum L value should be

calculated before Cmin and after Re (see Inductor Selection

below). Example: Re = 20m

Ω,Vnom=5V, ∆Vc_s = 160mV,

∆Ic_s = 3A, L = 8µH

Generally speaking, Cmin decreases with decreasing Re,

∆Ic_s, and L, but with increasing Vnom and ∆Vc_s.

20046213

FIGURE 9. Available Output Voltage Range

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