LAN9250 datasheet(49/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 49

LAN9250

To determine when the host interface is functional, the Byte Order Test Register (BYTE_TEST) should be polled. Once

the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in

the Hardware Configuration Register (HW_CFG) or the Power Management Control Register (PMT_CTRL) can be

polled to determine when the device is fully awake.

For both automatic and manual wake-up, the Device Ready (READY) bit will go high once the device is returned to

power savings state D0 and the PLL has re-stabilized. The PM_MODE and PM_SLEEP_EN fields in the Power Man-

agement Control Register (PMT_CTRL) will also clear at this point.

Under normal conditions, the device will wake-up within 2 ms.

6.3.5

POWER MANAGEMENT REGISTERS

6.3.5.1

Power Management Control Register (PMT_CTRL)

This read-write register controls the power management features and the PME pin of the device. The ready state of the

device be determined via the Device Ready (READY) bit of this register.

Offset:

084h

Size:

32 bits

Note:

This register can be read while the device is in the reset or not ready / power savings states without leaving

the host interface in an intermediate state. If the host interface is in a reset state, returned data may be

invalid.

It is not necessary to read all four bytes of this register. DWORD access rules do not apply to this register.

Bits

Description

Type

Default

31:29

Power Management Mode (PM_MODE)

This register field determines the chip level power management mode that

will be entered when the Power Management Sleep Enable

(PM_SLEEP_EN) bit is set.

000: D0

001: D1

010: D2

011: D3

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Writes to this field are ignored if Power Management Sleep Enable

(PM_SLEEP_EN) is also being written with a 1.

This field is cleared when the device wakes up.

R/W/SC

000b

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