LAN9250 datasheet(84/421 Pages) MICROCHIP

84 / 421 page

LAN9250

DS00001913A-page 84

 2015 Microchip Technology Inc.

8-BIT READ WITH SUPPRESSED ALEHI

The address is latched sequentially from AD[7:0]. A read on AD[7:0] follows. AD[15:8] pins are not used or driven. The

lower address is then updated to access the other BYTEs.

8-BIT WRITE

The address is latched sequentially from AD[7:0]. A write on AD[7:0] follows. AD[15:8] pins are not used or driven. The

cycle is repeated for the other BYTEs of the DWORD.

FIGURE 9-9:

MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT READS

WITHOUT ALEHI

FIGURE 9-10:

MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT WRITE

AD[15:8]

ALELO

ALEHI

AD[7:0]

Address Low

Address High

Data 7:0

Optional

Address+1 Low

Data 15:8

Optional

Hi-Z

Address+2 Low

Data 23:16

Optional

Address+3 Low

Data 31:24

Optional

ALELO

ALEHI

Address Low

Address High

Data 7:0

Optional

Address+1 Low Address High

Data 15:8

Optional

Address+2 Low Address High

Data 23:16

Address+3 Low Address High

Data 31:24

Hi-Z

Optional

AD[15:8]

AD[7:0]

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