UPSD323X datasheet(17/176 Pages) STMICROELECTRONICS

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µPSD323X

ARCHITECTURE OVERVIEW

Memory Organization

The

µPSD323X Devices’s standard 8032 Core

has separate 64KB address spaces for Program

memory and Data Memory. Program memory is

where the 8032 executes instructions from. Data

memory is used to hold data variables. Flash

memory can be mapped in either program or data

space. The Flash memory consists of two flash

memory blocks: the main Flash (1 or 2Mbit) and

the Secondary Flash (256Kbit). Except during

flash memory programming or update, Flash

memory can only be read, not written to. A Page

64K bytes address space. Refer to the PSD Mod-

ule for details on mapping of the Flash memory.

The 8032 core has two types of data memory (in-

ternal and external) that can be read and written.

The internal SRAM consists of 256 bytes, and in-

cludes the stack area.

The SFR (Special Function Registers) occupies

the upper 128 bytes of the internal SRAM, the reg-

isters can be accessed by Direct addressing only.

There are two separate blocks of external SRAM

inside the

µPSD323X Devices: one 256 bytes

block is assigned for DDC data storage. Another

8K bytes resides in the PSD Module that can be

mapped to any address space defined by the user.

Figure 5. Memory Map and Address Space

Registers

The 8032 has several registers; these are the Pro-

gram Counter (PC), Accumulator (A), B Register

(B), the Stack Pointer (SP), the Program Status

Word (PSW), General purpose registers (R0 to

R7), and DPTR (Data Pointer register).

Figure 6. 8032 MCU Registers

AI06635

SECONDARY

FLASH

MAIN

32KB

128KB

256KB

FFFF

(DDC)

8KB

256B

INT. RAM

EXT. RAM

Addressing

Indirect

Direct

Addressing

Direct

SFR

Internal RAM Space

(256 Bytes)

FF00

External RAM Space

(MOVX)

Flash Memory Space

AI06636

Accumulator

B Register

Stack Pointer

Program Counter

Program Status Word

General Purpose

Data Pointer Register

PCH

DPTR(DPH)

PCL

PSW

R0-R7

DPTR(DPL)

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