LP2975 datasheet(17/19 Pages) NSC

17 / 19 page

Application Hints (Continued)

This application can also be improved by adding a feed-

forward capacitor. C

F will add both a zero fzf and pole fpf to

the gain plot (see graph

LOW ESR CORRECTED WITH

FEED-FORWARD).

The crossover frequency f

c is now about 10 kHz. If CF is se-

lected so that f

zf is about 5 kHz, and fpf is about 20 kHz

(which means V

OUT = 5V), the phase margin will be consid-

erably improved. Calculating out all the poles and zeroes,

the phase margin is increased from 9˚ to 43˚ (adequate for

good stability).

EXCESSIVE GATE CAPACITANCE: Higher values of gate

capacitance shift the pole f

pg to lower frequencies, which can

cause stability problems (see previous section

GATE CA-

PACITANCE POLE FREQUENCY). As shown in the graph

fpg vs. CEFF, the pole fpg will likely fall somewhere between

40 kHz and 500 kHz. How much phase shift this adds de-

pends on the crossover frequency f

The effect of gate capacitance becomes most important at

high values of ESR for the output capacitor (see graph

HIGH

ESR UNSTABLE WITHOUT FEED-FORWARD). Higher val-

ues of ESR increase f

c, which brings fpg more into the posi-

tive gain portion of the curve. As f

pg moves to a lower fre-

quency

(corresponding

higher

values

gate

capacitance), this effect becomes even worse.

This points out why FET’s should be selected with the lowest

possible gate capacitance: it makes the design more tolerant

of higher ESR values on the output capacitor.

The use of a feed-forward capacitor C

F will help reduce ex-

cess phase shift due to f

pg, but its effectiveness depends on

output voltage (see next section).

LOW OUTPUT VOLTAGE AND C

The feed-forward capacitor C

F will provide a positive phase

shift (lead) which can be used to cancel some of the excess

phase lag from any of the various poles present in the loop.

However, it is important to note that the effectiveness of C

decreases with output voltage.

This is due to the fact that the frequencies of the zero f

zf and

pole f

pf get closer together as the output voltage is reduced

(see equations in section

FEED-FORWARD COMPENSA-

TION).

F is more effective when the pole-zero pair are farther

apart, because there is less self cancellation. The net benefit

in phase shift provided by C

F is the difference between the

lead (positive phase shift) from f

zf and the lag (negative

phase shift) from f

pf which is present at the crossover fre-

quency f

c. As the pole and zero frequency approach each

other, that difference diminishes to nothing.

The amount of phase lead at f

C provided by CF depends

both on the f

zf/fpf ratio and the location of fz with respect to fc.

To illustrate this more clearly, a graph is provided which

shows how much phase lead can be obtained for V

OUT =

12V, 5V, and 3.3V (see graph

PHASE LEAD PROVIDED BY

CF).

The most important information on the graph is the fre-

quency range of f

zf which will provide the maximum benefit

(most positive phase shift):

For V

OUT = 12V: 0.1 fc < fz < 1.0 fc

For V

OUT = 5V: 0.2 fc < fz < 1.2 fc

For V

OUT = 3.3V: 0.2 fc < fz < 1.3 fc

It’s also important to note how the maximum available phase

shift that C

F can provide drops off with VOUT. At 12V, more

than 50˚ can be obtained, but at 3.3V less than 30˚ is pos-

sible. The lesson from this is that higher voltage designs are

more tolerant of phase shifts from both f

pg (the gate capaci-

tance pole) and incorrect placement of f

z (which means the

output capacitor ESR is not at its nominal value). At lower

values of V

OUT, these parameters must be more precisely

selected since C

F can not provide as much correction.

GENERAL DESIGN PROCEDURE

Assuming that V

IN,VOUT, and RL are defined:

Low ESR Unstable without Feed-Forward

DS100034-30

Low ESR Corrected with Feed-Forward

DS100034-32

Phase Lead Provided by C

DS100034-33

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