DIR1701

SLAS331 – APRIL 2001

7

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system clock output (continued)

–30

–25

–20

–15

–10

–5

0

5

100

1 k

10 k

100 k

f – Frequency – Hz

Figure 2. Jitter Attenuator Characteristics With Specified Loop Filter

Table 2. Selectable Crystal Oscillators

SYSTEM CLOCK fS

CRYSTAL

BRSEL CONNECTED TO

128

12 MHz

CSBIT

256

12 MHz

OPEN or DGND

384

12 MHz

BFRAME

512

16 MHz

BFRAME

Table 3. System Clock Selection

SCF1

SCF0

SYSTEM CLOCK

LOW

LOW

128 fS

LOW

HIGH

256 fS

HIGH

LOW

384 fS

HIGH

HIGH

512 fS

Table 4. System Clock and Data Output Operation

CONDITIONS

CLOCK AND DATA OUTPUTS

S/PDIF DATA

SCKO

BCKO

LRCKO

DOUT

BRATE

UNLOCK

CS. UR BIT

AD. EMFLG

After RESET

Unknown

(128, 256, 384, 512 fS)

Unknown

(64 fS)

Unknown

(1 fS)

MUTE

LOW

HIGH

LOW

LOW

YES

PLL

(128, 256, 384, 512 fS)

PLL

(64 fS)

PLL

(1 fS)

DATA

DETECT

LOW

DATA

DATA

NO

HOLD†

(128, 256, 384, 512 fS)

HOLD†

(64 fS)

HOLD†

(1 fS)

MUTE

HOLD†

HIGH

HOLD†

HOLD†

† Holds the latest tracked frequency.