DIR1701

SLAS331 – APRIL 2001

9

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relation between audio-data-output timing and PLL condition indicator timing

When the analog PLL is still unlocked and the S/PDIF signal starts, after at least ten rising edges, the S/PDIF

decoder can detect the incoming S/PDIF signal. The DOUT pin becomes LOW (MUTE) until the analog PLL

decoder detects that incoming S/PDIF signal has stopped, UNLOCK goes HIGH at the next LRCKO transition.

SCKO keeps its frequency at the latest tracked bit rate.

When S/PDIF signal is not present after removal of reset, the frequency of the DIR1701 audio clocks (SCKO,

BCKO, LRCKO) is not known.

2

1

Mute

L

H

31

32

Mute

Unlock

Lock

PLL

Condition

UNLOCK

LRCKO

BCKO

DOUT

Figure 4. Relation Between Audio Data Output Timing and UNLOCK Flag Timing