| Datenblatt-Suchmaschine für elektronische Bauteile |
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PC87311AVF Datenblatt(PDF) 28 Page - National Semiconductor (TI) |
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PC87311AVF Datenblatt(HTML) 28 Page - National Semiconductor (TI) |
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28 / 78 page ![]() 40 FDC Command Set Description (Continued) Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector VERSION Command Phase 00010000 Result Phase 10010000 WRITE DATA Command Phase MT MFM 0 0 0 1 0 1 IPS X X X X HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Length Data Length Execution Phase Data is transferred from the system to the controller via DMA or Non-DMA modes and written to the disk Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector WRITE DELETED DATA Command Phase MT MFM 0 0 1 0 0 1 IPS X X X X HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Length Data Length Execution Phase Data is transferred from the system to the controller via DMA or Non-DMA modes and written to the disk Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector 42 COMMAND DESCRIPTION 421 Configure Command The Configure Command will control some operation modes of the controller It should be issued during the initialization of the FDC after power up The function of the bits in the Configure registers are described below These bits are set to their default values after a hardware reset The value of each bit after a software reset is explained The default val- ue of each bit is denoted by a ‘‘bullet’’ to the left of each item EIS Enable Implied Seeks Default after a software reset 0 e Implied seeks disabled through Configure command Implied seeks can still be enabled through the Mode command when EIS e 0 (default) 1 e Implied seeks enabled for a read write scan or veri- fy operation A seek and sense interrupt operation will be performed prior to the execution of the read write scan or verify operation The IPS bit does not need to be set 28 |
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