PC87311AVF datasheet(41/78 Pages) NSC

41 / 78 page

50 FDC Functional Description (Continued)

DRQ DACK and TC It is through this microprocessor inter-

face that the floppy controller receives commands transfers

data and returns status information

52 MODES OF OPERATION

The FDC has three modes of operation PC-AT mode PS2

mode and Model 30 mode which are determined by the

state of the IDENT pin and MFM pin IDENT can be tied

directly to VDD or GND The MFM pin must be tied high or

low with a 10 kX resistor (there is an internal 40 kX –50 kX

resistor on the MFM pin) The state of these pins is interro-

gated by the controller during a chip reset to determine the

mode of operation See Section 30 Register Description for

more details on the register set used for each mode of oper-

ation After chip reset the state of IDENT can be changed

to change the polarity of DENSEL (see Section 20 Pin De-

scription)

PC-AT Mode

(IDENT tied high MFM is a don’t care) The

PC-AT register set is enabled The DMA enable bit in the

Digital Output Register becomes valid (IRQ6 and DRQ can

be TRI-STATE) TC and DENSEL become active high sig-

nals (defaults to a 525

floppy drive)

PS2 Mode

(IDENT tied low MFM pulled high internally)

This mode supports the PS2 Models 506080 configura-

tion and register set The DMA enable bit in the Digital Out-

put Register becomes a don’t care (IRQ6 and DRQ signals

will always be valid) TC and DENSEL become active low

signals (default to 35

floppy drive)

Model 30 Mode

(IDENT tied low MFM pulled low exter-

nally) This mode supports the PS2 Model 30 configuration

and register set The DMA enable bit in the Digital Output

becomes

valid

(IRQ6

and

DRQ

can

TRI-STATE) TC is active high and DENSEL becomes ac-

tive low (default to 35

floppy drive)

53 CONTROLLER PHASES

The FDC has three separate phases of a command the

Command Phase the Execution Phase and the Result

Phase Each of these controller phases will determine how

data is transferred between the floppy controller and the

host microprocessor In addition when no command is in

progress the controller is in the Idle Phase or Drive Polling

Phase

531 Command Phase

During the Command Phase the mP writes a series of bytes

to the Data Register The first command byte contains the

opcode for the command and the controller will know how

many more bytes to expect based on this opcode byte The

remaining command bytes contain the particular parameters

required for the command The number of command bytes

will vary for each particular command All the command

bytes must be written in the order specified in the Command

Description Table The Execution Phase starts immediately

after the last byte in the Command Phase is written Prior to

performing the Command Phase the Digital Output Register

should be set and the data rate should be set with the Data

Rate Select Register or Configuration Control Register

The Main Status Register controls the flow of command

bytes and must be polled by the software before writing

each Command Phase byte to the Data Register Prior to

writing a command byte the RQM bit (D7) must be set and

the DIO bit (D6) must be cleared in the MSR After the first

command byte is written to the Data Register the CMD

PROG bit (D4) will also be set and will remain set until the

last Result Phase byte is read If there is no Result Phase

the CMD PROG bit will be cleared after the last command

byte is written

A new command may be initiated after reading all the result

bytes from the previous command If the next command

requires selecting a different drive or changing the data rate

the DOR and DSR or CCR should be updated If the com-

mand is the last command then the software should dese-

lect the drive

Note

As a general rule the operation of the controller core is independent

of how the mP updates the DOR DSR and CCR The software must

ensure that the manipulation of these registers is coordinated with the

controller operation

532 Execution Phase

During the Execution Phase the disk controller performs

the desired command Commands that involve data trans-

fers such as read write or format operation will require the

P to write or read data to or from the Data Register at this

time Some commands such as a Seek or Recalibrate will

control the readwrite head movement on the disk drive dur-

ing the Execution Phase via the disk interface signals The

execution of other commands does not involve any action

by the mP or disk drive and consists of an internal operation

by the controller

If there is data to be transferred between the mP and the

controller during the Execution there are three methods

that can be used DMA mode interrupt transfer mode and

software polling mode The last two modes are called the

Non-DMA modes The DMA mode is used if the system has

a DMA controller This allows the mP to do other tasks while

the data transfer takes place during the Execution Phase If

the Non-DMA mode is used an interrupt is issued for each

byte transferred during the Execution Phase Also instead

of using the interrupt during Non-DMA mode the Main

Status Register can be polled by software to indicate when

a byte transfer is required All of these data transfer modes

will work with the FIFO enabled or disabled

5321 DMA ModeFIFO Disabled

The DMA mode is selected by writinga0tothe DMA bit in

the Specify command and by setting the DMA enabled bit

(D3) in the DOR With the FIFO disabled a DMA request

(DRQ) is generated in the Execution Phase when each byte

is ready to be transferred The DMA controller should re-

spond to the DRQ with a DMA acknowledge (DACK) and a

read or write strobe The DRQ will be cleared by the leading

edge of the active low DACK input signal After the last byte

is transferred an interrupt is generated indicating the begin-

ning of the Result Phase During DMA operations the chip

select input (CS) must be held high The DACK signal will

act as the chip select for the FIFO in this case and the state

of the address lines A2 – A0 is a don’t care The Terminal

Count (TC) signal can be asserted by the DMA controller to

terminate the data transfer at any time Due to internal gat-

ing TC is only recognized when DACK is low

PC-AT Mode

When in the PC-AT interface mode with the

FIFO disabled the controller will be in single byte transfer

mode That is the system will have one byte time to service

a DMA request (DRQ) from the controller DRQ will be deas-

serted between each byte

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