TP3071 datasheet(9/26 Pages) NSC

9 / 26 page

Programmable Functions (Continued)

Three registers must be programmed in COMBO II to fully

configure the Hybrid Balance Filter as follows:

invert/non-invert cancellation signal;

select/de-select Hybal2 filter section;

attenuator setting.

set Hybal1 to 2nd order or 1st order;

pole and zero frequency selection.

program zero frequency in Hybal2 filter.

Standard filter design techniques may be used to model the

echo path (see

Equation (1)) and design a matching hybrid

balance filter configuration. Alternatively, the frequency re-

sponse of the echo path can be measured and the hybrid

balance filter designed to replicate it.

A Hybrid Balance filter design guide and software optimiza-

tion program are available under license from National Semi-

conductor Corporation; order TP3077SW.

Applications Information

Figure 3 shows a typical application of the TP3071 together

with a typical monolithic SLIC. Four of the IL latches are con-

figured as outputs to control the relay drivers on the SLIC,

while IL4 is an input for the Supervision signal.

POWER SUPPLIES

While the pins of the TP3070 COMBO II devices are well

protected against electrical misuse, it is recommended that

the standard CMOS practice of applying GND to the device

before any other connections are made should always be

followed. In applications where the printed circuit card may

be plugged into a hot socket with power and clocks already

present, extra long pins on the connector should be used for

ground and V

BB. In addition, a Schottky diode should be con-

nected between V

BB and ground.

To minimize noise sources, all ground connections to each

device should meet at a common point as close as possible

to the device GND pin in order to prevent the interaction of

ground return currents flowing through a common bus im-

pedance. Power supply decoupling capacitors of 0.1 µF

should be connected from this common device ground point

to V

CC and VBB as close to the device pins as possible. VCC

and V

BB should also be decoupled with Low Effective Series

Resistance Capacitors of at least 10 µF located near the

card edge connector.

Further guidelines on PCB layout techniques are provided in

Application Note AN-614, “ COMBO II™ Programmable PCM

CODEC/Filter Family Application Guide”.

DS008635-5

FIGURE 2. Simplified Diagram of Hybrid Balance Circuit

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