Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at T

correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals

specified at V

All timing parameters are measured at V

See Definitions and Timing Conventions section for test methods information.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

SERIAL CONTROL PORT TIMING

t

DSD

Delay Time, CS Low

Applies Only if Separate

80

ns

to CO (CI/O) Valid

CS used for Byte 2

−40˚C to +85˚C (TP3070-X)

100

ns

t

DDZ

Delay Time, CS or 9th CCLK

High to CO (CI/O) High

Impedance

Applies to Earlier of CS High or 9th

CCLK High

15

80

ns

INTERFACE LATCH TIMING

t

SLC

Setup Time, IL to

Interface Latch Inputs Only

100

ns

CCLK 8 of Byte 1

t

HCL

Hold Time, IL Valid from

50

ns

8th CCLK Low (Byte 1)

t

DCL

Delay Time CCLK 8 of

Interface Latch Outputs Only

200

ns

Byte2toIL

C

MASTER RESET PIN

t

WMR

Duration of

1

µs

Master Reset High

Note 11: Applies only to MCLK Frequencies

Timing Diagrams

DS008635-8

FIGURE 4. Non Delayed Data Timing Mode

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