AT91EB55 datasheet(12/37 Pages) ATMEL

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Circuit Description

4-2

AT91EB55 Evaluation Board User Guide

4.3

Memories

The schematics in Figures 3 and 9 in "Appendix B – Schematics" show one

AT49BV16X4 2-Mbyte 16-bit Flash, one AT24C512 64-Kbyte EEPROM, one AT25256

32-Kbyte EEPROM, two 128K/512K x 8 SRAM devices and four AT45DB321 4-Mbyte

serial data Flash devices.

The SPI devices are accessible through a 4 to 16 line decoder and by using the Chip

Select Decode feature of the AT91 SPI peripheral (PCSDEC bit of the SPI Mode

Note:

The AT91EB55 is fitted with two 128K x 8 SRAM devices and one AT45DB321 serial

DataFlash device (U21).

The AT91EB55 may be fitted with a Flash using either an AT49BV1604 (CB18 should

be closed) or an AT49BV1614 (CB18 should be open).

Strap JP1 shown on the schematic is used to select which part of 1-Mbyte of the flash is

to be accessed. This is to enable users to flash download their application in the second

part of the flash and to boot on it.

4.4

ADC and DAC

Peripheral

Connections

Two of the ADC and DAC channels are loop-backed together: DA0 on AD4 and DA1 on

AD0.

Two 2.5V voltage reference devices are fitted on the board and connected to the

DAVREF and ADVREF inputs, See Figures 6 in "Appendix B – Schematics". The user

can fit other voltage reference value devices from this family (REF19x from Analog

Devices) as the footprints are compatible.

A temperature sensor (LM61: figure 6 in "Appendix B – Schematics") is connected to the

AD1 input and is placed near the 32.768 kHz crystal quartz. It enables the user to take

into account the frequency drift due to temperature evolutions using a software program.

The V

DDCORE with a resistor bridge (10 kΩ) provides the following value:

This voltage can be measured by AD2 input and allows the user to select the running

clock accordingly.

4.5

Power and

Crystal Quartz

The board features two quartz crystals: a 32.768 kHz one connected to the RTC low-

power oscillator of the AT91M55800A and a 16 MHz one connected to the main

oscillator.

The AT91M55800A Master Clock can be derived from the 32.768 kHz crystal quartz or

the 16 MHz crystal quartz depending on the programming of the APMC registers. The

on-chip oscillators together with one PLL-based frequency multiplier and the prescaler

results in a programmable Master Clock between 500 Hz and 33 MHz.

Components for the PLL filter are fitted by default on the board (Figure 6 in "Appendix B

– Schematics"). They are calculated to provide a 32 MHz (multiplier factor of 2 and set-

tling time of 160 µs) Master Clock frequency.

The Voltage Regulator provides 3.3V to the board and will light the red POWER LED

(D11) when operating.

This Voltage Regulator can be turned off by using the APMC shutdown feature when the

JP7 jumper is closed. See Figure 8 in "Appendix B – Schematics." A wake-up push but-

ton (S1) is provided to exit this mode. Alternatively, the user can program a RTC alarm

to awake the voltage regulator.

VDDCORE

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