AD9656EBZ datasheet(34/47 Pages) AD

34 / 47 page

Data Sheet

AD9656

Rev. A | Page 33 of 46

Frame and Lane Alignment Monitoring and Correction

Frame alignment monitoring and correction is part of the JESD204B

specification. The 16-bit word requires two octets to transmit all

the data. The two octets (MSB and LSB), where F = 2, make up

a frame. During normal operating conditions, frame alignment

is monitored via alignment characters, which are inserted under

certain conditions at the end of a frame. Table 16 summarizes the

conditions for character insertion, along with the expected characters

under the various operation modes. If lane synchronization is

enabled, the replacement character value depends on whether

the octet is at the end of a frame or at the end of a multiframe.

Based on the operating mode, the receiver can ensure that it is

still synchronized to the frame boundary by correctly receiving

the replacement characters.

Digital Outputs and Timing

The AD9656 has differential digital outputs that power up by

default. The driver current is derived on chip and sets the output

current at each output equal to a nominal 3 mA. Each output

presents a 100 Ω dynamic internal termination to reduce

unwanted reflections.

The AD9656 digital outputs can interface with custom ASICs and

FPGA receivers, providing superior switching performance in

noisy environments. Single point to point network topologies are

recommended with a single differential 100 Ω termination resistor

placed as close to the receiver logic as possible.

For receiver inputs that are self biased, or with input common

mode requirements not within the bounds of the AD9656

DRVDD supply, use an ac-coupled connection as shown in

Figure 71. Place a 0.1 μF series capacitor on each output pin and

use a 100 Ω differential termination close to the receiver side. The

100 Ω differential termination results in a nominal 600 mV p-p

differential swing at the receiver. In the case where the receiver

inputs are not self biased, single-ended 50 Ω terminations can be

used. When single-ended terminations are used, the termination

voltage (VRXCM) must be chosen to match the input requirements

of the receiver.

100Ω

50Ω

100Ω

DIFFERENTIAL

TRACE PAIR

SERDOUTx+

DRVDD

VRXCM

SINGLE-ENDED

TERMINATION

DIFFERENTIAL

TERMINATION

SERDOUTx–

VCM = Rx VCM

OUTPUT SWING = 600mV p-p

DIFFERENTIAL

0.1µF

RECEIVER

Figure 71. AC-Coupled Digital Output Termination Example

For receivers with input common mode voltage requirements

matching the output common mode voltage (DRVDD/2) of the

AD9656, a dc-coupled connection can be used. The common

mode of the digital output automatically biases itself to half of

DRVDD (0.9 V for DRVDD = 1.8 V) (see Figure 72).

100Ω

DIFFERENTIAL

TRACE PAIR

DRVDD

VCM = DRVDD/2

OUTPUT SWING = 600mV p-p

DIFFERENTIAL

RECEIVER

SERDOUTx+

SERDOUTx–

Figure 72. DC-Coupled Digital Output Termination Example

If there is no far-end receiver termination, or if there is poor

differential trace routing, timing errors can result. To avoid such

timing errors, it is recommended that the trace length be less than

six inches and the differential output traces be close together and of

equal lengths.

Figure 73 shows an example of the digital output data eye and

time interval error (TIE) jitter histogram and bathtub curve for

an AD9656 lane running at 6.4 Gbps.

The maximum allowable data rate per lane is 8 Gbps. In some

configurations, the AD9656 maximum conversion rate is limited

by the maximum allowable data rate. The output data rate per

lane is calculated as follows:

Rate

Sample

Rate

Data

)

(





where M (number of converters), N (resolution), and

L (Number of lanes) are defined in the JESD204B Overview

section. For example, with M = 4, N = 16, and L = 1; the sample

rate is limited to 100 Msps.

Additional SPI options allow the user to further increase the

output driver voltage swing of all four outputs to drive longer

trace lengths (see Register 0x15 in Table 19). The power

dissipation of the DRVDD supply increases when this option is

used. See the Memory Map section for more information.

The format of the output data is twos complement by default.

To change the output data format to offset binary, see the

Memory Map section and Register 0x14 in Table 19.

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