AD9656EBZ datasheet(45/47 Pages) AD

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AD9656

Data Sheet

Rev. A | Page 44 of 46

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting system level design and layout of the AD9656, it

is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD9656, it is recommended to

use separate 1.8 V supplies: one supply for analog (AVDD), a

separate shared supply for the digital outputs (DRVDD), and the

digital (DVDD). DRVDD must be kept at the same voltage as

DVDD. SVDD can be shared with any of the other supplies if

1.8 V SPI operation is desired. The designer can use several

different decoupling capacitors to cover both high and low

frequencies. Locate these capacitors close to the point of entry

at the PCB level and close to the pins of the device with

minimal trace length.

When using the AD9656, a single PCB ground plane is sufficient.

With proper decoupling and smart partitioning of the PCB

analog, digital, and clock sections, optimum performance is

easily achieved.

CLOCK STABILITY CONSIDERATIONS

When powered on, the AD9656 enters an initialization phase

during which an internal state machine sets up the biases and

the registers for proper operation. During the initialization

process, the AD9656 requires a stable clock. If the ADC clock

source is not present or not stable during ADC power-up, it

disrupts the state machine and causes the ADC to start up in an

unknown state. To correct this, an initialization sequence must

be reinvoked after the ADC clock is stable by issuing a digital

reset via Register 0x08. In the default configuration (internal

VREF, ac-coupled input) where VREF and VCM are supplied by the

ADC itself, a stable clock during power-up is sufficient. In the

case where VREF and/or VCM are supplied by an external source,

these, too, must be stable at power-up; otherwise, a subsequent

digital reset via Register 0x08 is needed. Interruption of the

sample clock during operation and changes in sample rate also

necessitate a digital reset. The pseudo code sequence for a

digital reset is as follows:

SPI_Write (0x08, 0x03);

# Digital Reset

SPI_Write (0x08, 0x00);

# Normal Operation

EXPOSED PAD THERMAL HEAT SLUG

RECOMMENDATIONS

It is mandatory that the exposed pad on the underside of the ADC

connect to analog ground (AGND) to achieve the best electrical

and thermal performance. A continuous, exposed (no solder mask)

copper plane on the PCB must mate to the AD9656 exposed

pad, Pin 0.

The copper plane must have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow

through the bottom of the PCB. Fill or plug these vias with

nonconductive epoxy.

To maximize the coverage and adhesion between the ADC and

the PCB, overlay a silkscreen to partition the continuous plane

on the PCB into several uniform sections. This partitioning

prevents the solder from pooling and provides several tie points

between the ADC and the PCB during the reflow process. Using

one continuous plane with no partitions guarantees only one tie

point between the ADC and the PCB. See the evaluation board

for a PCB layout example. For detailed information about the

packaging and PCB layout of chip scale packages, refer to the

AN-772 Application Note, A Design and Manufacturing Guide

for the Lead Frame Chip Scale Package (LFCSP).

VCM

Decouple the VCM pin to ground with a 0.1 µF capacitor.

REFERENCE DECOUPLING

Externally bypass the VREF pin to ground with a low ESR,

1.0 µF capacitor in parallel with a low ESR, 0.1 µF ceramic

capacitor.

SPI PORT

When the full dynamic performance of the converter is required,

do not activate the SPI port. Because the SCLK, CSB, and SDIO

signals are typically asynchronous to the ADC clock, noise from

these signals can degrade converter performance. If the on-board

SPI bus is used for other devices, it may be necessary to provide

buffers between this bus and the AD9656 to keep these signals

from transitioning at the converter input pins during critical

sampling periods.

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