Data Sheet M11657EJBV0DS

17

Write Cycle Timing Chart 3 (CE2 Controlled)

Data in

High impedance

Address (Input)

CE2 (Input)

I/O (Input)

High

impedance

/CE1 (Input)

/WE (Input)

Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.