ADAU1772BCPZ-R7 datasheet(31/117 Pages) AD

31 / 117 page

ADAU1772

Data Sheet

Rev. C | Page 30 of 116

SYSTEM CLOCKING AND POWER-UP

CLOCK INITIALIZATION

The ADAU1772 can generate its clocks either from an externally

provided clock or from a crystal oscillator. In both cases, the on-

board PLL can be used or the clock can be fed directly to the

core. When a crystal oscillator is used, it is desirable to use a

12.288 MHz crystal, and the crystal oscillator function must be

enabled in the COREN bit (Address 0x0000). If the PLL is used,

it should always be set to output 24.576 MHz. The PLL can be

bypassed if a clock of 12.288 MHz or 24.576 MHz is available in

the system. Bypassing the PLL saves system power.

The CC_MDIV and CC_CDIV bits should not be changed after

setup, but the CLKSRC bit can be switched while the core is

running.

The CC_MDIV and CC_CDIV bits should be set so that the core

and internal master clock are always 12.288 MHz; for example,

when using a 24.576 MHz external source clock or if using the

PLL, it is necessary to use the internal divide by 2 (see Table 11).

Table 11. Clock Configuration Settings

CC_MDIV

CC_CDIV

Description

Divide PLL/external clock by 1. Use these

settings for a 12.288 MHz direct input clock

source.

Divide PLL/external clock by 2. Use these

settings for a 24.576 MHz direct input clock

source or if using the PLL.

PLL Bypass Setup

On power up, the ADAU1772 comes out of an internal reset

after 12 ms. The rate of the internal master clock must be set

properly using the CC_MDIV bit in the clock control register

(Address 0x0000). When bypassing the PLL, the clock associated

with MCLKIN must be either 12.288 MHz or 24.576 MHz. The

internal master clock of the ADAU1772 is disabled until the

COREN bit is asserted.

PLL Enabled Setup

The core clock of the ADAU1772 is disabled by the default

setting of Bit COREN and should remain disabled during the

PLL lock acquisition period. The user can poll the LOCK bit to

determine when the PLL has locked. After lock is acquired, the

ADAU1772 can be started by asserting the COREN bit. This bit

enables the core clock for all the internal blocks of the ADAU1772.

To program the PLL during initialization or reconfiguration of

the codec, the following procedure must be followed:

1. Ensure that PLL_EN (Bit 7, Address 0x0000) is set low.

2. Set/reset the PLL control registers (Address 0x0001 to

Address 0x0005).

3. Enable the PLL using the PLL_EN bit.

4. Poll the PLL lock bit in Register 0x0006.

5. Set the COREN bit in Register 0x0000 after PLL lock is

acquired.

Control Port Access During Initialization

During the lock acquisition period, only Register 0x0000 to

or write to any other register is prohibited until the core clock

enable bit and the lock bit are both asserted.

After the CORE_RUN bit (Address 0x0009) is set high, the

DAC_SOURCE0 and DAC_SOURCE1 register bits should not

be changed. If these bits must be changed after the ADAU1772

is running, the CORE_RUN bit first must be disabled.

PLL

The PLL uses the MCLKIN signal as a reference to generate

the core clock. The PLL settings are set in Register 0x0000 to

must be set for either integer or fractional mode. The PLL can

accept input frequencies in the range of 8 MHz to 27 MHz.

Figure 76. PLL Block Diagram

Input Clock Divider

Before reaching the PLL, the input clock signal goes through an

integer clock divider to ensure that the clock frequency is within

a suitable range for the PLL. The X bits in the PLL_CTRL4 register

(Bits[2:1], Address 0x0005) sets the PLL input clock divide ratio.

Integer Mode

Integer mode is used when the clock input is an integer multiple

of the PLL output.

For example, if MCLKIN = 12.288 MHz and (X + 1) = 1, and

fS = 48 kHz, then

PLL Required Output = 24.576 MHz

R/2 = 24.576 MHz/12.288 MHz = 2

where R/2 = 2 or R = 4.

In integer mode, the values set for N and M are ignored.

Table 12 lists common integer PLL parameter settings for

48 kHz sampling rates.

Fractional Mode

Fractional mode is used when the clock input is a fractional

multiple of the PLL output.

For example, if MCLKIN = 13 MHz, (X + 1) = 1, and

fS = 48 kHz, then

PLL Required Output = 24.576 MHz

(1/2) × (R + (N/M)) = 24.576 MHz/13 MHz = (1/2) × (3 +

(1269/1625))

where:

R = 3.

N = 1269.

M = 1625.

MCLK

÷X

× (R + N/M)

TO PLL

CLOCK DIVIDER

ADAU1772BCPZ-R7 Datenblatt(PDF) 31 Page - Analog Devices

ADAU1772BCPZ-R7 Datenblatt(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL