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ADAU1772

Data Sheet

Rev. C | Page 44 of 116

SELF-BOOT

The ADAU1772 boots up from an EEPROM over the I2C bus

when the SELFBOOT pin is set high at power-up and the PD

pin is set high. The state of the SELFBOOT pin is checked only

when the ADAU1772 comes out of a reset via the PD pin, and

the EEPROM is not used after a self-boot is complete. During

booting, ensure that there is a stable DVDD in the system. The

PD pin should remain high during the self-boot operation. The

master SCL clock output from the ADAU1772 is derived from

the input clock on XTALI/MCLKIN. A divide-by-64 circuit

ensures that the SCL output frequency during the self-boot

operation is never greater than 400 kHz for most input clock

frequencies. With the external master clock to the ADAU1772

being between 12 MHz and 27 MHz, the SCL frequency ranges

from 176 kHz to 422 kHz. If the self-boot EEPROM is not rated

for operation above 400 kHz, be sure to use a master clock that

is no faster than 25.6 MHz.

Table 25 shows the list of instructions that are possible during

an ADAU1772 self-boot. The 0x01 and 0x05 instruction bytes

are used to load the register, program, and parameter settings.

EEPROM Size

The self-boot circuit is compatible with an EEPROM that has a

2-byte address. For most EEPROM families, a 2-byte address is

used on devices that are 32 kB or larger. The EEPROM must be

set to Address 0x50. Examples of two compatible EEPROMs

include Atmel AT24C32D and STMicroelectronics M24C32-F.

Table 24 lists the maximum necessary EEPROM size, assuming

that there is 100% utilization of the program and parameters

(both banks). There is inherently some overhead for instructions

to control the self-boot procedure.

Table 24. Maximum EEPROM Size

ADAU1772

Memory Blocks

Word Size

(Bytes per

Word)

Words

Total EEPROM

Space Requirement

(Bytes)

Program

Bank 0 Parameters

160 (32 × 5)

640

Bank 1 Parameters

160

640

Registers

Total Bytes

1409

CRC

An 8-bit CRC validates the content of the EEPROM. This CRC is

strong enough to detect single error bursts of up to eight bits in size.

The terminate self-boot instruction (0x00 instruction byte) must

be followed by a CRC byte. The CRC is generated using all of the

EEPROM bytes from Address 0x0000 to the last 0x00 instruction

byte. The polynomial for the CRC is



If the CRC is incorrect or if an unrecognized instruction byte is

read during self-boot, the boot process is immediately stopped

and restarted after a 250 ms delay (for a 12.288 MHz input clock).

When SigmaStudio is used, the CRC byte is generated auto-

matically when a configuration is downloaded to the EEPROM.

Delay

The delay instruction (0x02 instruction byte) delays by the

16-bit setting × 2048 clock cycles.

Boot Time

The time to self-boot the ADAU1772 from an EEPROM can be

calculated using the following equation:

Boot Time = 64/MCLK Frequency × Total Bytes + Wait Time

The self-boot operation starts after 16,568 clock cycles are seen on

the XTALI/MCLKIN pin after PD is set high. With a 12.288 MHz

clock, this corresponds to approximately a 1.35 ms wait time

from power-up. This delay ensures that the crystal used for

generating the master clock has ramped up to a stable oscillation.

Table 25. EEPROM Self-Boot Instructions

Instruction

Byte ID

Instruction Byte

Description

Following Bytes

0x00

End self-boot

CRC

0x01

Write multibyte length

minus two bytes, starting

at target address

Length (high byte),

length (low byte),

address (high byte),

address (low byte),

data (0), data (1), ...

data (length – 3)

0x02

Delays by the 16-bit setting

× 2048 clock cycles

Delay (high byte),

delay (low byte)

0x03

No operation

None

0x04

Wait for PLL lock

None

0x05

Write single byte to target

address

Address (high byte),

address (low byte), data

Figure 91. A List of Example Self-Boot EEPROM Instructions

0x1A

0x2B

0x3C

0x04

0x03

0x00

DATA

(0)

DATA

(1)

DATA

(LENGTH – 3)

PLL LOCK

NO OP

END

PROGRAM RAM DATA

0x02

0x00

0x04

0x01

0x00

0x05

0x00

0x80

DELAY

(HIGH BYTE)

DELAY

(LOW BYTE)

WRITE

LENGTH

(HIGH BYTE)

LENGTH

(LOW BYTE)

ADDRESS

(HIGH BYTE)

ADDRESS

(LOW BYTE)

DELAY LENGTH

LENGTH

PROGRAM RAM ADDRESS

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