AD6650BBCZ datasheet(34/45 Pages) AD

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AD6650

Rev. A | Page 33 of 44

Table 18. Memory Map

Reg.

(Hex)

Mnemonic

Bit

Width

Description

Additional Information

Code

Result

Clock Divider Control

Power-up value is 1’b1.

Bypass

Divide-by-2

PLL Register 0

PLL Control Register 0.

See Table 19

PLL Register 1

PLL Control Register 1.

See

Table 20

PLL Register 2

PLL Control Register 2.

See Table 21

PLL Register 3

PLL Control Register 3.

See Table 22

Clamp Control

Various VGA control signals.

Power-up value is 6’b100011

Code

Gain (dB)

5 to 2: Tweak Gain

+1.6 dB

Provides ±1.6 dB of additional gain in VGA in

0.2 dB steps.

+1.4 dB

+1.2 dB

+0.2 dB

0 dB

−0.2 dB

−1.2 dB

−1.4 dB

Code

Result

1: Clamp Disable B

Enable clamp

Disables clamps at the output of the VGA for

Channel B.

Disable clamp

0: Clamp Disable A

Enable clamp

Disables clamps at the output of the VGA for

Channel A.

Disable clamp

Reserved

Reserved.

Must be written 8’b00000000

Reserved

Reserved.

Must be written 8’b00000000

Reserved

Reserved.

Must be written 8’b00010001

Reserved

Must be written 0.

Power-up value is 2’b00

Coarse DC Correction

Coarse dc correction control registers.

Power-up value is 4’b0000

Code

Result

3: Cal Now B

Disabled

Recalibrate

Calibrate coarse dc correction for the

Channel B. Coarse dc correction occurs

automatically at start-up if Bit 0 of the

AutoCalibration control register is set high.

2: Cal Now A

Disabled

Calibrate coarse dc correction for the

Channel A. Coarse dc correction occurs

automatically at start-up if Bit 0 of the

AutoCalibration control register is set high.

Recalibrate

1: PN_EN

Disabled

Enables the PN sequence generator to test

the digital block.

Enable PN

sequence

generator

Code

Result

0: Coarse DCC Enable

Disabled

Enables coarse DCC. This register must be

held high during start-up sequence for

coarse dc correction to occur.

DCC enabled

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