AD6677 datasheet(8/48 Pages) AD

8 / 48 page

AD6677

Data Sheet

Rev. C | Page 8 of 48

Parameter

Temperature

Min

Typ

Max

Unit

Low Level Output Voltage (VOL)

Full

IOL = 2.0 mA

Full

0.25

IOL = 1.6 mA

Full

0.2

IOL = 50 µA

Full

0.05

Pull-up.

Needs an external pull-up.

Pull-down.

Compatible with JEDEC standard JESD8-7A.

SWITCHING SPECIFICATIONS

Table 4.

Parameter

Symbol

Temperature

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Conversion Rate1

Full

250

MSPS

SYSREF± Setup Time to Rising Edge CLK±2

tREFS

Full

300

SYSREF± Hold Time from Rising Edge CLK±2

tREFH

Full

SYSREF± Setup Time to Rising Edge RFCLK±2

tREFSRF

Full

400

SYSREF± Hold Time from Rising Edge RFCLK±2

tREFHRF

Full

CLK± Pulse Width High

tCH

Divide by 1 Mode, DCS Enabled

Full

1.8

2.0

2.2

Divide by 1 Mode, DCS Disabled

Full

1.9

2.0

2.1

Divide by 2 Mode Through Divide by 8 Mode

Full

0.8

Aperture Delay

Full

1.0

Aperture Uncertainty (Jitter)

Full

0.16

ps rms

DATA OUTPUT PARAMETERS

Data Output Period or Unit Interval (UI)

Full

20 × fS

Seconds

Data Output Duty Cycle

25°C

Data Valid Time

25°C

0.78

PLL Lock Time

tLOCK

25°C

µs

Wake-Up

Time (Standby)

25°C

µs

Time ADC (Power-Down)3

25°C

250

Time Output (Power-Down)4

25°C

Subclass 0: SYNCINB± Falling Edge to First Valid K.28

Characters (Delay Required for Rx CGS Start)

Full

Multiframes

Subclass 1: SYSREF± Rising Edge to First Valid K.28

Characters (Delay Required for SYNCB± Rising

Edge/Rx CGS Start)

Full

Multiframes

CGS Phase K.28 Characters Duration

Full

Multiframe

Pipeline Delay

JESD204B (Latency)

Full

Cycles5

Additional Pipeline Latency with NSR Enabled

Full

Cycles

Fast Detect (Latency)

Full

Cycles

Lane Rate

Full

Gbps

Uncorrelated Bounded High Probability (UBHP) Jitter

Full

Random Jitter at 5 Gbps

Full

1.7

ps rms

Output Rise/Fall Time

Full

Differential Termination Resistance

25°C

100

Ω

Out of Range Recovery Time

Full

Cycles

Conversion rate is the clock rate after the divider.

Refer to Figure 3 for timing diagram.

Wake-up time ADC is defined as the time required for the ADC to return to normal operation from power-down mode.

Wake-up time output is defined as the time required for JESD204B output to return to normal operation from power-down mode.

Cycles refers to ADC conversion rate cycles.

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