AD6677 datasheet(11/48 Pages) AD

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Data Sheet

AD6677

Rev. C | Page 11 of 48

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF

THE PACKAGE PROVIDES THE GROUND REFERENCE FOR

AVDD. THIS EXPOSED PAD MUST BE CONNECTED TO AGND

FOR PROPER OPERATION.

RST

24 DNC

23 PDWN

22 CS

21 SCLK

20 SDIO

19 FD

18 DGND

17 DVDD

RFCLK

CLK–

CLK+

AVDD

SYSREF+

SYSREF–

AVDD

AD6677

TOP VIEW

(Not to Scale)

Figure 4. Pin Configuration (Top View)

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

4, 7, 26, 27, 30, 31, 32

AVDD

Supply

Analog Power Supply (1.8 V Nominal).

9, 18

DGND

Ground

Ground Reference for DVDD.

10, 17

DVDD

Supply

Digital Power Supply (1.8 V Nominal).

DRGND

Ground

Ground Reference for DRVDD.

DRVDD

Supply

JESD204B PHY Serial Output Driver Supply (1.8 V Nominal). Note

that the DRVDD power is referenced to the AGND plane.

DNC

Do Not Connect.

EPAD (AGND)

Ground

Expose Pad. The exposed thermal pad on the bottom of the package

provides the ground reference for AVDD. This exposed pad must be

connected to AGND for proper operation.

ADC Analog

RFCLK

Input

ADC RF Clock Input.

CLK−

Input

ADC Nyquist Clock Input—Complement.

CLK+

Input

ADC Nyquist Clock Input—True.

VCM

Output

Common-Mode Level Bias Output for Analog Inputs. Decouple this

pin to ground using a 0.1 µF capacitor.

VIN−

Input

Differential Analog Input (Negative).

VIN+

Input

Differential Analog Input (Positive).

ADC Fast Detect Output

Output

Fast Detect Indicator (CMOS Levels).

Digital Inputs

SYSREF+

Input

JESD204B LVDS SYSREF Input—True.

SYSREF−

Input

JESD204B LVDS SYSREF Input—Complement.

SYNCINB+

Input

JESD204B LVDS Sync Input—True/JESD204B CMOS Sync Input.

SYNCINB−

Input

JESD204B LVDS Sync Input—Complement.

Data Outputs

SERDOUT0−

Output

CML Output Data—Complement.

SERDOUT0+

Output

CML Output Data—True.

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