OX16CF950 datasheet(42/60 Pages) ETC

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OXCF950 DATA SHEET V1.1

OXFORD SEMICONDUCTOR LTD.

logic [11] ⇒ DTR# pin is configured to drive the active-

high enable pin of an external RS485 buffer.

In this configuration, the DTR# pin will be

forced high whenever the transmitter is not

empty (LSR[6]=0), otherwise DTR# pin is

low.

If the user sets ACR[4], then the DTR# line is controlled by

the status of the transmitter empty bit of LCR. When

ACR[4] is set, ACR[3] is used to select active high or active

low enable signals. In half-duplex systems using RS485

protocol, this facility enables the DTR# line to directly

control the enable signal of external 3-state line driver

buffers. When the transmitter is empty the DTR# would go

inactive once the SOUT line returns to it’s idle marking

state.

ACR[5]: 950 mode trigger levels enable

logic 0 ⇒

Interrupts and flow control trigger levels are

as described in FCR register and are

compatible with 16C650/16C750 modes.

logic 1 ⇒

950 specific enhanced interrupt and flow

control trigger levels defined by RTL, TTL,

FCL and FCH are enabled.

ACR[6]: ICR read enable

logic 0 ⇒

The Line Status Register is readable.

logic 1 ⇒

The Indexed Control Registers are readable.

Setting this bit will map the ICR set to the LSR location for

reads. During normal operation this bit should be cleared.

ACR[7]: Additional status enable

logic 0 ⇒

Access to the ASR, TFL and RFL registers

is disabled.

logic 1 ⇒

Access to the ASR, TFL and RFL registers

is enabled.

When ACR[7] is set, the MCR and LCR registers are no

longer readable but remain writable, and the TFL and RFL

registers replace them in the memory map for read

operations. The IER register is replaced by the ASR

this bit set during normal operation, since MCR, LCR and

IER do not generally need to be read.

6.11.4 Transmitter Trigger Level ‘TTL’

The TTL register is located at offset 0x04 of the ICR

Whenever 950 trigger levels are enabled (ACR[5]=1), bits 4

and 5 of FCR are ignored and an alternative arbitrary

transmitter interrupt trigger level can be defined in the TTL

transmitter interrupt trigger facility. In 950 mode, a priority

level 3 interrupt occurs indicating that the transmitter buffer

requires more characters when the interrupt is not masked

(IER[1]=1) and the transmitter FIFO level falls below the

value stored in the TTL register. The value 0 (0x00) has a

special meaning. In 950 mode when the user writes 0x00

to the TTL register, a level 3 interrupt only occurs when the

FIFO and the transmitter shift register are both empty and

the SOUT line is in the idle marking state. This feature is

particularly useful to report back the empty state of the

transmitter after its FIFO has been flushed away.

6.11.5 Receiver Interrupt. Trigger Level ‘RTL’

The RTL register is located at offset 0x05 of the ICR

Whenever 950 trigger levels are enabled (ACR[5]=1), bits 6

and 7 of FCR are ignored and an alternative arbitrary

receiver interrupt trigger level can be defined in the RTL

receiver interrupt trigger facility as opposed to the limited

trigger levels available in 16C650 and 16C750 devices. It

enables the system designer to optimise the interrupt

performance hence minimising the interrupt overhead.

In 950 mode, a priority level 2 interrupt occurs indicating

that the receiver data is available when the interrupt is not

masked (IER[0]=1) and the receiver FIFO level reaches the

value stored in this register.

6.11.6 Flow Control Levels ‘FCL & FCH’

The FCL and FCH registers are located at offsets 0x06 and

0x07 of the ICR respectively

Enhanced software flow control using XON/XOFF and

hardware flow control using RTS#/CTS# and DTR#/DSR#

are available when 950 mode trigger levels are enabled

(ACR[5]=1). Improved flow control threshold levels are

offered using Flow Control Lower trigger level (‘FCL’) and

Flow Control Higher trigger level (‘FCH’) registers to

provide a greater degree of flexibility when optimising the

flow control performance. Generally, these facilities are

only available in Enhanced mode.

In 650 mode, in-band flow control is enabled using the EFR

receiver FIFO exceeds the upper trigger level defined by

FCR[7:6] as described in section 6.4.1. An XON is then

sent when the FIFO is read down to the lower fill level. The

flow control is enabled and the appropriate mode selected

using EFR[3:0].

In 950 mode, the flow control thresholds defined by

FCR[7:6] are ignored. In this mode threshold levels are

programmed using FCL and FCH. When in-band flow

control is enabled (defined by EFR[3:0]) and the receiver

FIFO level (‘RFL’) reaches the value programmed in the

FCH register, an XOFF is transmitted to stop the flow of

serial data . The flow is resumed when the receiver FIFO

fill level falls to below the value programmed in the FCL

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