LTC2335-16 datasheet(29/40 Pages) LINER

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LTC2335-16

233516f

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POWER CONSIDERATIONS

The LTC2335-16 provides four power supply pins: the

positive and negative high voltage power supplies (VCC

and VEE), the 5V core power supply (VDD) and the digital

input/output (I/O) interface power supply (OVDD). As long

as the voltage difference limits of 10V ≤ VCC – VEE ≤ 38V

are observed, VCC and VEE may be independently biased

anywhere within their own individual allowed operating

ranges, including the ability for either of the supplies to be

tied directly to ground. This feature enables the common

mode input range of the LTC2335-16 to be tailored to the

specificapplication’srequirements.TheflexibleOVDDsup-

ply allows the LTC2335-16 to communicate with CMOS

logic operating between 1.8V and 5V, including 2.5V and

3.3V systems. When using LVDS I/O mode, the range of

OVDD is 2.375V to 5.25V.

Power Supply Sequencing

The LTC2335-16 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2335-16 has

an internal power-on-reset (POR) circuit which resets the

converter on initial power-up and whenever VDD drops

below 2V. Once the supply voltage re-enters the nominal

supply voltage range, the POR reinitializes the ADC. No

conversions should be initiated until at least 10ms after

a POR event to ensure the initialization period has ended.

Whenemployingtheinternalreferencebuffer,allow200ms

forthebuffertopowerupandrechargetheREFBUFbypass

capacitor. Any conversion initiated before these times will

produce invalid results.

TIMING AND CONTROL

CNV Timing

The LTC2335-16 sampling and conversion is controlled

by CNV. A rising edge on CNV transitions the S/H circuits

from track mode to hold mode, sampling the input signals

and initiating a conversion. Once a conversion has been

started, it cannot be terminated early except by resetting

the ADC, as discussed in the Reset Timing section. For

optimum performance, drive CNV with a clean, low jitter

signal and avoid transitions on data I/O lines leading up

to the rising edge of CNV. Additionally, for best crosstalk

performance,avoidhighslewratesontheanaloginputsfor

100ns before and after the rising edge of CNV. Converter

status is indicated by the BUSY output, which transitions

low-to-high at the start of each conversion and stays high

untiltheconversioniscomplete. OnceCNVisbroughthigh

to begin a conversion, it should be returned low between

40ns and 60ns later or after the falling edge of BUSY to

minimizeexternaldisturbancesduringtheinternalconver-

sion process. The CNV timing required to take advantage

of the reduced power nap mode of operation is described

in the Nap Mode section.

Internal Conversion Clock

The LTC2335-16 has an internal clock that is trimmed

to achieve a maximum conversion time of 550ns. With

a minimum acquisition time of 420ns, throughput per-

formance of 1Msps is guaranteed without any external

adjustments. The LTC2335-16 is a multiplexed ADC and

converts one channel per CNV edge, taking a minimum

of 1μs per conversion. Thus, while scanning N channels

(N = 1 to 8), a complete scan takes at least N μs and the

maximum per-channel throughput is 1/N Msps/ch.

Nap Mode

The LTC2335-16 can be placed into nap mode after a con-

versionhasbeencompletedtoreducepowerconsumption

between conversions. In this mode a portion of the device

circuitry is turned off, including circuits associated with

sampling the analog input signals. Nap mode is enabled

applicaTions inForMaTion

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