MCP6281 datasheet(11/32 Pages) MICROCHIP

11 / 32 page

 2004 Microchip Technology Inc.

DS21811D-page 11

MCP6281/2/3/4/5

4.0

APPLICATION INFORMATION

The MCP6281/2/3/4/5 family of op amps is manufac-

tured

using

Microchip's

state-of-the-art

CMOS

process. This family is specifically designed for low-

cost, low-power and general purpose applications.

The low supply voltage, low quiescent current and

wide bandwidth makes the MCP6281/2/3/4/5 ideal for

battery-powered applications.

4.1

Rail-to-Rail Inputs

The MCP6281/2/3/4/5 op amp is designed to prevent

phase reversal when the input pins exceed the supply

voltages. Figure 4-1 shows the input voltage exceeding

the supply voltage without any phase reversal.

FIGURE 4-1:

The MCP6281/2/3/4/5 Show

No Phase Reversal.

The input stage of the MCP6281/2/3/4/5 op amps use

two differential CMOS input stages in parallel. One

operates at low common mode input voltage (VCM),

while the other operates at high VCM. With this

topology, the device operates with VCM up to 0.3V

above VDD and 0.3V below VSS. The Input Offset Volt-

age (VOS) is measured at VCM =VSS –0.3V and

VDD + 0.3V to ensure proper operation.

Input voltages that exceed the absolute maximum

voltage (VSS – 0.3V to VDD + 0.3V) can cause

excessive current to flow into or out of the input pins.

Current beyond ±2 mA can cause reliability problems.

Applications that exceed this rating must be externally

limited with a resistor, as shown in Figure 4-2.

FIGURE 4-2:

Input Current Limiting

Resistor (RIN).

4.2

Rail-to-Rail Output

The output voltage range of the MCP6281/2/3/4/5 op

amp is VDD –15mV (min.) and VSS +15mV (max.)

when

RL =10kΩ is connected to VDD/2 and

VDD = 5.5V. Refer to Figure 2-16 for more information.

4.3

Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. A unity-gain buffer (G = +1) is the most

sensitive to capacitive loads, though all gains show the

same general behavior.

When driving large capacitive loads with these op

amps (e.g., > 100 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-3) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will generally be lower than the bandwidth

with no capacitive load.

FIGURE 4-3:

Output Resistor, RISO

stabilizes large capacitive loads.

Figure 4-4 gives recommended RISO values for differ-

ent capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit's noise gain. For non-inverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

-1

-15

-14

-13

-12

-11

-10

-9

-8

-7

-6

-5

Time (1 ms/div)

VDD = 5.0V

G = +2 V/V

VIN

VOUT

Minimum expected V

()

–

2 mA

------------------------------------------------------------------------------

≥

Maximum expected V

() V

–

2 mA

----------------------------------------------------------------------------------

≥

VIN

RIN

VOUT

–

MCP628X

VIN

RISO

VOUT

–

MCP628X

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