MCP6281 datasheet(12/32 Pages) MICROCHIP

12 / 32 page

MCP6281/2/3/4/5

DS21811D-page 12

 2004 Microchip Technology Inc.

FIGURE 4-4:

Recommended RISO Values

for Capacitive Loads.

After selecting RISO for your circuit, double-check the

resulting

frequency

response

peaking

and

step

response overshoot. Modify RISO's value until the

response is reasonable. Bench evaluation and simula-

tions with the MCP6281/2/3/4/5 SPICE macro model

are helpful.

4.4

MCP628X Chip Select (CS)

The MCP6283 and MCP6285 are single and dual op

amps with Chip Select (CS), respectively. When CS is

pulled high, the supply current drops to 0.7 µA (typ) and

flows through the CS pin to VSS. When this happens,

the amplifier output is put into a high-impedance state.

By pulling CS low, the amplifier is enabled. If the CS pin

is left floating, the amplifier may not operate properly.

Figure 1-1 shows the output voltage and supply current

response to a CS pulse.

4.5

Cascaded Dual Op Amps

(MCP6285)

The MCP6285 is a dual op amp with Chip Select (CS).

The Chip Select input is available on what would be the

non-inverting input of a standard dual op amp (pin 5).

This pin is available because the output of op amp A

connects to the non-inverting input of op amp B, as

shown in Figure 4-5. The Chip Select input, which can

be connected to a microcontroller I/O line, puts the

device in Low-power mode. Refer to Section 4.4

“MCP6283/5 Chip Select (CS)”.

FIGURE 4-5:

Cascaded Gain Amplifier.

The output of op amp A is loaded by the input imped-

ance of op amp B, which is typically 1013

Ω||6pF, as

specified in the DC specification table (Refer to

Section 4.3 “Capacitive Loads” for further details

regarding capacitive loads).

The common mode input range of these op amps is

specified in the data sheet as VSS – 300 mV and

VDD + 300 mV. However, since the output of op amp A

is limited to VOL and VOH (20 mV from the rails with a

10 k

Ω load), the non-inverting input range of op amp B

is limited to the common mode input range of

VSS + 20 mV and VDD –20mV.

4.6

Supply Bypass

With this family of operational amplifiers, the power

supply pin (VDD for single-supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good, high-frequency performance. It also needs a

bulk capacitor (i.e., 1 µF or larger) within 100 mm to

provide large, slow currents. This bulk capacitor can be

shared with other analog parts.

4.7

PCB Surface Leakage

In applications where low input bias current is critical,

Printed Circuit Board (PCB) surface-leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 1012

Ω. A 5V difference would

cause 5 pA of current to flow, which is greater than the

MCP6281/2/3/4/5 family’s bias current at 25°C (1 pA,

typ.).

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 4-6.

100

1,000

100

1,000

10,000

Normalized Load Capacitance; C

L/GN (pF)

GN = 1 V/V

N = 2 V/V

N ≥ 4 V/V

VINA+

VOUTB

MCP6285

VINA–

VOUTA/VINB+

VINB–

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